High-Speed Circuit Design Principles:Additional Techniques for Performance Improvement

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Additional Techniques for Performance Improvement

Very high-speed static dividers often can be made to clock at higher frequencies by small modifications in the circuit. Two of these, shunt peaking and “keep-alive” current, will be discussed in this section.

The method of shunt peaking is an old one, dating from the vacuum tube era, where high-frequency performance was lacking [5,11]. A zero is added to the amplifier transfer function by including a series inductance with the collector or drain resistance. This can in principle, compensate for a lower frequency pole and extend bandwidth and improve risetime. Figure 74.11 presents an example of an amplifier with shunt peaking. This approach can be extended to the load resistances of an MSFF frequency divider. Walker and Wallmann [11] show that the risetime can be significantly increased, but at the expense of some overshoot. Some overshoot can generally be tolerated in high-speed digital circuits, so the approach has been used successfully to improve speed. Defining a parameter M in Eq. (74.34),

High-Speed Circuit Design Principles-0031

Table 74.5 shows that risetime can be reduced by a factor of 2.1 if about 11% overshoot is acceptable.

Static frequency dividers were designed and fabricated in a 60 GHz fT SiGe and 170 GHz fTInP HBT technologies as described in Ref. [8]. Versions with and without shunt peaking inductance were evaluated. In both cases, a moderate increase in maximum clock frequency was observed as shown in Table 74.6.

A second technique to improve maximum clock frequency is the use of keep-alive current. The keep-alive current, a small current source, IKA, is connected to the emitters of the Q3, Q4 differential pair in Figure 74.10. Recall that the (iii)–(iv) transition determines the circuit delay. The data inputs, D and DBAR, steer current in the Q3, Q4 pair. Since the D and DBAR inputs have settled to a stable value before the clock switches Q1, it is the clock transition that controls the delay of the track stage. By keeping a small but constant current on the Q3/Q4 emitter node, the VBE change produced by the clock transition is reduced. This has the effect of increasing GM and consequently CD , but the charging resistance looking into the emitter node is decreased by the same amount. The net benefit comes from reducing the charging time of CBE since that is not strongly dependent on the voltage swing. A detailed explanation of this effect can be found in Ref. [8].

High-Speed Circuit Design Principles-0032

High-Speed Circuit Design Principles-0033

Static frequency dividers with and without keep-alive current were also fabricated and tested [8]. The results shown in Table 74.6 also indicate that a small improvement in maximum clock frequency can be gained by the combined use of the shunt peaking and keep-alive current methods.

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