Content-Addressable Memory:CAM Word Circuits.

CAM Word Circuits

In the general CAM architecture, the word match circuit is designed using dynamic CMOS circuit design to improve data match performance and hardware cost. In the dynamic CMOS circuit design as shown in Figure 56.5, the circuit operation can be separated into two phases: precharge phase (CLK = VSS) and evaluation phase (CLK = VDD). In the precharge phase, owing to the input signal CLK being VSS, the pull-up transistor M1 is turned on and the pull-down transistor M2 is turned off. In this case, a charge current Ip is created by the pull-up transistor M1 to charge the parasitic capacitance CL, and the output node OUT is rising up to VDD. In the evaluation phase, as a result of the input signal CLK being VDD, the pull-up transistor M1 is turned off and the pull-down transistor M2 is turned on. In this case, the output node OUT is conditionally falling down to VSS depending on the function of the N-logic block. If the N-logic block contains a short path from the output node OUT to the pull-down transistor M2 during evaluation phase, then a discharge current Ie is created by the N-logic block and the pull-down transistor M2 to discharge the parasitic capacitance CL, and the output node OUT is falling down to VSS. Otherwise, the parasitic capacitance CL is floating and the output node OUT remains at VDD.

Based on the dynamic CMOS circuit design, the dynamic word match circuit as illustrated in Figure 56.6 is used to realize data match operation. With n-bit stored data, the dynamic word match circuit usually consists of the number of n CAM cells, the valid bit circuit (VBC), the dynamic circuit controller (DCC), and the match line sense amplifier (MLSA). The VBC is used to indicate the availability of data stored in the word match circuit and the DCC is utilized to control dynamic circuit operation. If the stored state in the VBC is invalid, then the match-line ML is falling down to VSS indicating that the stored data is invalid, and the stored data is always mismatched with the search data. Otherwise, the word match circuit performs a data match function. In the output stage, the MLSA is adopted to amplify the voltage swing of the match-line ML for improving the circuit speed. To identify the match result of the word match circuit, the comparison results of all CAM cells in each word match circuit are collected, and the

different collection approaches result in different circuit features. In the following three sections, some popular word match circuit designs are described.

NOR-Type Word Match Circuit

In the NOR-type word match circuit as shown in Figure 56.7 [12], this design collects the resultant transistors M2 of all CAM cells in parallel connection. In this circuit, if the stored data match the search data, then every bit in the search data matches with every corresponding bit in the stored data, else at least one bit in the stored data is mismatched with the corresponding bit in the search data. In addition, referring to the truth table of the nine-transistor BCAM cell shown in Table 56.1, if the comparison result is matched, then the resultant transistor M3 is turned on, else the resultant transistor M3 is turned off. According to the results mentioned above, if the search data match with the data stored in the NOR-type word match circuit, then all the resultant transistors M2 are turned off, else at least one resultant transistor M2 is turned on.

During the data search cycle, the dynamic operation of NOR-type word match circuit can be separated into the precharge phase and evaluation phase. In the precharge phase, the DCC turns on the pull-up transistor M1 to precharge the parasitic capacitance CL by a charge current Ip. In this situation, if the stored data are matched with the search data, then the match-line ML is VDD, owing to all the resultant transistors M2 being turned off and the pull-up transistor M1 being turned on. Otherwise, the match- line ML is less than VDD, as a result of the pull-up transistor M1 and at least one resultant transistor M2 being turned on, simultaneously. For this reason, the NOR-type word match circuit consumes static power dissipation when the stored data mismatch the search data. In the evaluation phase, the DCC turns off the pull-up transistor M1. In this situation, if the stored data match the search data, then the match-line ML is kept to VDD, owing to all the resultant transistors M2 and the pull-up transistor M1 being turned-off, simultaneously. Otherwise, the match-line ML is falling down to VSS by a discharge current Ie, as a result of at least one resultant transistor M2 being turned on and the pull-up transistor M1 being turned off. For this reason, the NOR-type word match circuit consumes dynamic power dissipation when the stored data mismatch the search data. As in the above-mentioned circuit operation, the NOR-type word match circuit consumes static and dynamic power dissipations simultaneously when the stored data mismatch the search data. Generally, in each data search cycle, almost all data stored in the CAM array are mismatched with the search data. Therefore, the NOR-type word match circuit consumes large amounts of static and dynamic search power dissipations.

In the NOR-type word match circuit, since the design collects the resultant transistors M2 of all CAM cells in parallel connection, the longest pull-down path from the match-line ML to the ground node VSS contains only one transistor M2 that reduces the discharge time of the match-line ML during the evaluation phase. Therefore, the NOR-type word match circuit achieves high-speed data search performance. However, the parallel connection of transistors M2 results in a large parasitic capacitance CL that consumes large dynamic search power dissipation when the stored data mismatch the search data.

NAND-Type Word Match Circuit

One of the most popular techniques for reducing search power dissipation in the word match circuit is the one using the NAND-type structure as shown in Figure 56.8 [14]. In the NAND-type word match circuit, this design collects the resultant transistors M2 of all the CAM cells in series connection. Moreover, the circuit operation of each CAM cell in the NAND-type word match circuit is opposite to that of the

NOR-type word match circuit. In the NAND-type word match circuit, if the comparison result is matched, then the resultant transistor M2 in the CAM cell is turned off, else the resultant transistor M2 in the CAM cell is turned on. Based on the NAND-type word match circuit design, if the stored data match the search data, then the resultant transistors M2 in all the CAM cells are turned on, else at least one resultant transistor M2 in the CAM cell is turned off.

During the data search cycle, the dynamic operation of NAND-type word match circuit can also be separated into the precharge phase and evaluation phase. In the precharge phase, the DCC turns on the pull-up transistor M1 to precharge the parasitic capacitance CL by a charge current Ip. In this situation, if the stored data are mismatched with the search data, then the match-line ML is VDD, owing to at least one resultant transistor M2 being turned off and the pull-up transistor M1 being turned on. Otherwise, the match-line ML is less than VDD, as a result of the pull-up transistor M1 and all the resultant transistors M2 are turned on, simultaneously. For this reason, the NAND-type word match circuit consumes static power dissipation when the stored data match the search data. In the evaluation phase, the DCC turns off the pull-up transistor M1. In this situation, if the stored data mismatch the search data, then the match-line ML is kept to VDD, owing to the pull-up transistor M1 and at least one resultant transistor M2 being turned off, simultaneously. Otherwise, the match-line ML is falling down to VSS by a discharge current Ie, as a result of all the resultant transistors M2 being turned on and the pull-up transistor M1 being turned off. Therefore, the NAND-type word match circuit consumes dynamic power dissipation when the stored data match the search data. As in the above-mentioned circuit operation, the NAND- type word match circuit consumes static and dynamic power dissipations simultaneously when the stored data match the search data. Since only a few data stored in the CAM array are matched with the search data during each data search operation, the NAND-type word match circuit saves large amounts of static and dynamic search power dissipations compared to the NOR-type word match circuit. In this circuit, since the design collects the resultant transistors M2 of all CAM cells in series connection and the longest pull-down path from the match-line ML to the ground node VSS contains all the transistors M2, the long pull-down path structure increases the discharge time of the match-line ML during the evaluation phase. Therefore, the operation speed of the NAND-type word match circuit is slower than that of the NOR-type word match circuit.

Selective Precharged Word Match Circuit

In the conventional word match circuit designs, the NOR-type circuit has high-speed and high-power features, while the NAND-type circuit has low-speed and low-power features. To achieve high-speed and low-power features simultaneously, a NOR-type and NAND-type combination word match circuit, called selective precharged word match circuit [13], is one of the best structures. In the selective precharged word match circuit as illustrated in Figure 56.9, the resultant transistors M3 of p CAM cells (where p CAM cells are a small subset of n CAM cells) are series connected in the pull-up path of the match-line ML, and the remaining (n - p) CAM cells are parallel connected in the pull-down path of the match- line ML. Moreover, the resultant transistor M3 of each CAM cell in the pull-up path is a PMOS transistor, while the resultant transistor M2 of each CAM cell in the pull-down path is an NMOS transistor. Therefore, if the comparison results of all CAM cells in the pull-up path are matched, then all the pull- up transistors M3 are turned on, else at least one pull-up transistor M3 is turned off. In contrast, if the comparison results of all the CAM cells in the pull-down path are matched, then all the pull-down transistors M2 are turned off, else at least one pull-down transistor M2 is turned on. In this design, a reset function is required to initiate dynamic circuit operation. To realize the reset function, a reset transistor M4 is parallel connected in the pull-down path of the match-line ML. The data search operation of this circuit is described as follows.

Initially, the word match circuit operates in a reset mode. In this mode, the input signal RST is assigned to VDD to turn on the reset transistor M4 and a discharge current IRST is generated by the turn-on transistor M4 to discharge the parasitic capacitance CL. As a result, the potential of the match-line ML is falling down to VSS. After that, the input signal RST is assigned to VSS to turn off the reset transistor M4 and the circuit is operated in dynamic operation. In the precharge phase, the pull-up transistor M1 is turned on by the DCC. In this phase, if the comparison results of all the CAM cells in the pull-up path are matched, then a charge current Ip is created by the turn-on transistors M1 and M3 to charge the

parasitic capacitance CL, and the potential of the match-line ML is rising up to VDD. Otherwise, the match-line ML is kept to VSS. In the evaluation phase, if the comparison results of all the CAM cells in the pull-down path are matched, then the potential of the match-line ML is fixed. Otherwise, a discharge current Ie is created by at least one turn-on transistor M2 to discharge the parasitic capacitance CL, and the potential of the match-line ML is falling down to VSS. To summarize the dynamic circuit operation addressed above, if the stored data match the search data (the comparison results of all the CAM cells are matched), then the potential of the match-line ML is VDD. Otherwise (the comparison result of at least one CAM cell is mismatched), the potential of the match-line ML is VSS.

In the selective precharged word match circuit, the search speed is dominated by the number of series- connected transistors M3 (in this case, the number of series connected transistors M3 is p) in the pull-up path of the match-line ML, since the charge time of the parasitic capacitance CL is proportional to the number of series-connected transistors M3 in the pull-up path of the match-line ML. Therefore, the p is as small as possible to improve search performance. In addition, the power dissipation of the selective precharged word match circuit is dominated by the number of parallel-connected transistors M2 (in this case, the number of parallel-connected transistors M2 is n - p) in the pull-down path of the match-line ML, since the discharge probability of the parasitic capacitance CL is proportional to the number of parallel-connected transistors M2 in the pull-down path of the match-line ML. For this reason, the p is as large as possible to reduce power dissipation. To summarize the above-mentioned circuit operation, the search speed and the power dissipation of the selective precharged word match circuit are between the NOR-type and NAND-type word match circuits. If p is set to 0, then the selective precharged word match circuit is similar to the NOR-type word match circuit. If p is set to n, then the selective precharged word match circuit is similar to the NAND-type word match circuit. Therefore, both the NOR-type and the NAND-type word match circuits are the special cases of the selective precharged word match circuit, and the selective precharged word match circuit can choose a suitable p value for diverse CAM applications.