Case Study: A Serial Pass Mode Architecture for BPC

By -
Case Study: A Serial Pass Mode Architecture for BPC

A simplified block diagram of the serial pass mode EBCOT tier-1 architecture [3,4] is presented in Figure 81.19. To begin, the “Memories” block actually contains three individual memories, each the same dimensions as the code-block and 1-bit per entry. The significant status memory (σ) maintains

VLSI Architectures for JPEG 2000 EBCOT-Design Techniques and Challenges-0084

VLSI Architectures for JPEG 2000 EBCOT-Design Techniques and Challenges-0085

information on the significance status of each bit in the current bit-plane of the code-block. The second memory, first refinement status memory (σmr), uses a single bit to indicate whether or not the coefficient has been processed during an earlier magnitude refinement pass. The final memory subblock, new significant status memory (σnew), contains the most recent updates to the coefficient’s significance status and is similar to σ. For example, once a coefficient is found significant, the corresponding bit in σnew is set to indicate its new significance status. At the start of a bit-plane, the contents of σnew are copied into σ to reflect all status changes that occurred in the previous bit-plane. Using the column-processing concept, the “neighbor processing” block reads the data from the memories and calculates H, V, and D for each bit in a column simultaneously. These values along with the significance information of the coefficient are used to determine which coefficients are coded during the current pass (NBC) and thus enable pixel skipping. The “context formation” block contains the circuitry for generating the context labels for those NBC bits. The control unit included several submodules that manage the operation of the entire architecture.

One obstacle encountered with column processing is that the state variable processing element (PE) produces the NC for each of the four coefficients in parallel. However, the PEs for context formation operate in serial. To resolve this discrepancy, the selector block uses the NBC information to serially choose which of the coefficients will be sent to the context formation PEs. It is possible to implement parallel processing in the context formation blocks; however, this requires several duplications of the hardware, which may be underutilized when only a few coefficients from a column are coded during a particular pass.

The components of this architecture were implemented using Synopsis and 0.5 µm technology. The results are shown in Table 81.3.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more