VLSI Architectures for Forward Error-Control Decoders:High-Speed Turbo Decoder Architectures

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High-Speed Turbo Decoder Architectures

The turbo code considered in this section is made up of two recursive systematic convolutional (RSC) encoders concatenated in parallel as shown in Figure 82.19. The bit sequences transferred from one encoder to the other are permuted by an interleaver. The decoder contains two SISO MAP decoders which are associated with the two RSC encoders as depicted in this figure. The decoding of the observed sequences is performed iteratively via the exchange of soft output information (L(u(k))) between the constituent decoders. The decoding process is repeated iteratively until an appropriate stopping criterion is satisfied.

The turbo decoder can be implemented via a serial architecture as shown in Figure 82.20, where one SISO MAP decoder is time-shared. Hence, increasing the throughput of the SISO MAP decoder directly leads to an overall improvement in throughput of the turbo decoder.

High-throughput turbo decoder architectures are designed using the MAP decoder architectures presented in Section 82.4.2. Table 82.1 summarizes the key parameters for the parallel, BIP, and look- ahead BIP architectures for two codes with encoder polynomials [5,7]8 (L = 16) and [13,15]8 (L = 32), with constraint length (encoder memory) K = 3 and 4, respectively. These parameters are obtained from

VLSI Architectures for Forward Error-Control Decoders-0125

an implementation using 2.5 V, 0.25 mm CMOS technology standard cell library using Synopsys Design Compiler-based synthesis, Cadence Silicon Ensemble-based place and route, and Pathmill-based postlayout simulations. The parallelization factor M = 2 for all the architectures. From Table 82.1, we see that the BIP-based turbo decoder architecture delivers the same speedup as compared to parallel processing with a comparatively smaller area. In particular, the BIP technique reduces the logic complexity nearly by a factor of M keeping the memory complexity the same as that of parallel processing. Further details can be found in Ref. [55].

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