Timing and Signal Integrity Analysis:Noise, Circuit Delays, and Timing Analysis.

Noise, Circuit Delays, and Timing Analysis

Circuit noise, especially crosstalk noise, significantly affects switching delays. Let us consider the example of Figure 63.16(a), where we are concerned about the propagation delay from A to C. In the absence of any coupling capacitances, the rising waveform at C is shown by the dotted line of Figure 63.16(b). However, if net 2 is switching in the opposite direction (node E is rising as in Figure 63.16(b)), then additional charge is pumped into net 1 due to the coupling capacitors causing the signals at nodes B1 and B2 to slow down. This in turn causes the inverter to switch later and causes the propagation delay from A to C to be much larger, as shown in the diagram. Note that if net 2 switched in the same direction as net 1, then the delay from A to C would be reduced. This implies that delays across gates and wires depend on the switching activity on adjacent coupled nets. Since coupling capacitances are a large fraction of the total capacitance of wires, this dependence will be significant and timing analysis should account

for this behavior. Using the same terminology as crosstalk noise analysis, we call the net whose delay is of primary interest (net 1 in the above example) the victim net and all the nets that are coupled to it are called aggressor nets.

A model that is commonly used to approximate the effect of coupling capacitors on circuit delays is to replace each coupling capacitor by a grounded capacitor of twice the value. This model is accurate only when the victim and aggressor nets are identical and the waveforms on the two nets are identical, but switching in opposite directions. For some cases, doubling the coupling capacitance may be pessi- mistic, but in many cases it is not — the effective capacitance is much more than twice the coupling capacitance. Note that the effect on the propagation delay due to coupling will be strongly dependent on how the aggressor waveforms are aligned with respect to each other and to the victim waveform. Hence, one of the main issues in finding the effect of noise on delay is to determine the aggressor alignments that cause the worst propagation delay.

A more accurate model for considering the effect of noise on delay is described by Dartu et al. [47]. In this approach, the gates are replaced by linearized models (e.g., the Thevenin model of the gate consists of a shifted ramp voltage source in series with a resistance). Once the circuit has been linearized, the principle of linear superposition is applied. The voltage waveform at the sink of the victim net is first obtained by assuming that all aggressors are “quiet.” Then the victim net is assumed to be quiet and each aggressor is switched one at a time and the resultant noise waveforms at the victim sink node is recorded. These noise waveforms are offset with respect to each other because of the difference in the delays between the aggressors to the victim sink node. Next, the aggressor noise waveforms are shifted such that the peaks get lined up and a composite noise waveform is obtained by adding the individual noise waveforms. The remaining issue is to align the composite noise waveform with the noise-free victim waveform to obtain the worst delay. This process is described in Figure 63.17, where we show the original noise-free waveform Vorig and the (composite) noise waveform Vnoise at the victim sink node. Then, the worst case is to align the noise such that its peak is at the time when Vorig = 0.5Vdd – VN , where VN is the peak noise [47,48]. The final waveform at C is marked Vfinal .

The impact of noise on delays and the impact of timing windows on noise analysis implies that one has to iterate between timing and noise analysis. There is no guarantee that this process will converge; in fact, one can come up with examples when the process diverges. This is one of the open issues in noise analysis.