Switched-Capacitor Filters:First-Order SC Stages

First-Order SC Stages

The Active SC Integrators

In Figure 62.8(a)–(c) the standard integrators normally used in SC designs are shown. For each integrator, the transfer function in the z-domain is reported, assuming that the input signal is sampled during phase f1 and is held to this value until the end of phase f2, while the output is read during phase f2.

The third integrator is called bilinear since it implements the bilinear mapping of the s-to-z transformation (s is the state variable in the continuous-time domain).

In all the above transfer functions, only capacitor ratios appear. For this reason the SC filter transfer functions are sensitive only to the capacitor ratios (i.e., to the capacitor matching) and independent of absolute capacitor value. This is a remarkable advantage of all the SC networks.

An important feature of all of these integrators is their insensitivity to parasitic capacitance. This can be verified observing that any parasitic capacitance connected to the capacitor left-hand plate is not connected to the virtual ground and therefore does not contribute to the amount of injected charge. In contrast, the stray capacitance connected to the capacitor right-hand armature could contribute to the charge transfer, but this capacitance is switched between two nodes (ground and virtual ground) at the same potential and thus no charge injection results.

The Summing Integrator

The SC operation is based on charge transfer. It is therefore easy to make weighted sum of multiple inputs by connecting different input branches to the same virtual ground. This concept is shown in the summing integrator of Figure 62.9. The transfer function from the three input signals to the output is given in Eq. (62.10).

If the integrating feedback capacitor (Cf ) is replaced by a feedback switched capacitor (Csw), the structure does not maintain memory of its past evolution and a simple summing amplifier is obtained. The resulting structure is shown in Figure 62.10, with the corresponding transfer function given in Eq. (62.11). This is the basic building block for the construction of SC filters implementing FIR frequency response [4].

The Active Damped SC Integrator

A damped integrator can be realized by connecting a damping switched capacitor (Cd) in parallel to the integrating capacitor (Cf ), as shown in Figure 62.11. Both inverting or noninverting circuits are possible, depending on the type of the input sampling structure. Eq. (62.12) is valid for the clock phases not in parenthesis, while Eq. (62.13) is valid for the clock phases within parenthesis.

A Design Example

As an example, the design of a damped SC integrator (Figure 62.11) is given. A possible design approach is to derive the capacitor values of the SC structure from the R and C values in the equivalent continuous-time prototype, which is shown in Figure 62.12, by Eq. (62.6). It results that Cs = Ts/Rs, and Cd = Ts/Rd. For instance, to have the pole frequency at 10 kHz with unitary DC gain, a possible solution is Rs = Rd = 159.15 kW, and Cf = 10 pF. Using Fs = 1 MHz, Cs = Cd = 0.628 pF.

The frequency response of the continuous-time and the SC damped integrator are shown in Figure 62.13(a).

Line I refers to the damped integrator of Figure 62.11, line II to a damped integrator with bilinear input branch (see Figure 62.8[c]), and line III to the active-RC integrator of Figure 62.11. In the passband the

frequency responses track very well. Increasing the input frequency, a difference becomes evident (as stated by the fact that Eq. (62.6) is valid for slowly variant signals). This is more pronounced if the frequency response is plotted up to 2Fs (see Figure 62.13[b]), where the periodic behavior of the sampled-data system frequency response is evident. Moreover, the key point of a sampled-data filter is the fact that the frequency response fixes the ratio between sampling frequency and pole frequency, i.e., with the above capacitor values the pole frequency is 10 kHz for Fs = 1 MHz, while it decreases to 1 kHz if Fs = 100 kHz is used (i.e., the ratio fp/Fs remains constant). For this reason the frequency response is plotted as a function of the normalized frequency f/Fs.

A limited stopband attenuation results for line I. This attenuation is improved using the bilinear input branch which implements a zero at Fs/2. This does not affect the frequency response in the passband, while a larger attenuation is obtained in the stopband (line II).

For the SC networks, the frequency response depends on capacitor ratios. Thus the above extracted capacitor value can be normalized to the lowest one (which will be the unit capacitance). For this first- order cell example, the normalized capacitor values are Cf = 15.92, and Cs = Cd = 1. The chosen value of the unit capacitance will not change the transfer function, while it will affect other filter features like die size, power consumption, and output noise.

In general, using Cf much higher than Cd results in such a small damping impedance, as it is the case of high-Q filters. This results in a large capacitor spread. In contrast, to have a small time constant requires to have Cs much smaller than Cf, and also in this case a large capacitor spread occurs. Since the unit capacitance cannot be smaller than a minimum technological value (to achieve a certain matching accuracy), a large capacitor spread means to have a large capacitor to be driven and so a large power to the opamp to operate. In addition a large chip area is also needed. Thus to avoid large capacitor spread, possible solutions are proposed as follows.