Nyquist-Rate ADC and DAC:ADC Design Considerations

ADC Design Considerations

In general, multi-step ADCs are made of cascaded low-resolution ADCs. Each low-resolution ADC stage provides a residue voltage for the subsequent stage, and the accuracy of the residue voltage limits the resolution of the converter. One of the residue amplifiers commonly used in CMOS is a switched-capacitor

MDAC, whose connections during two clock phases are illustrated in Figure 58.23 for an N-bit case [9]. An extra capacitor C is usually added to double the feedback capacitor size so that the residue voltage may remain within the full-scale range for digital correction.

Sampling Error Considerations

Since the ADC works on a sampled signal, the accuracy in sampling fundamentally limits the system perfor- mance. It is well known that the noise power to be sampled on a capacitor along with the signal is KT/C. It is inversely proportional to the sampling capacitor size. The sampled rms voltage noise is 64 mV with 1 pF, but decreases to 20 mV with 10 pF. For accurate sampling, sampling capacitors should be large, but sampling on large capacitors takes time. The speed of the ADC is fundamentally limited by the sampling KT/C noise. In sampling, there exists another important error source. Direct sampling on a capacitor suffers from switch feedthrough error due to the charge injection when switches are opened. A common way to reduce

this charge feedthrough error is to turn off the switches connected to the sampling capacitor top plate slightly earlier than the switches connected to the bottom plate. This is explained in Figure 58.24. Usually, the top plate is connected to the op-amp summing or comparator input node. The top plate is switched with one MOS transistor with a clock phase marked as F¢1 which makes a falling transition earlier than other clocks. The bottom plate is switched with a CMOS switch (both NMOS and PMOS) with clocks marked as F and`F1 . These clocks make falling transitions after the prime clock does. The net effect is that the feedthrough voltage stays constant because the top plate samples the same voltage repeatedly. The differential sampling using two capacitors symmetrically is known to provide the most accurate sampling known to date.

Unless limited by speed, the sampling error as well as the low-end spectrum of the sampled noise can be eliminated using a correlated double sampling (CDS) technique. The system has been used to remove the flicker noise or slowly-varying offset such as in charge-coupled device (CCD). The CDS needs two sampling clocks. The idea is to subtract the previously sampled sampling error from the new sample after one clock delay. The result is to null the sampling error spectrum at every multiple of the sampling frequency fs. The CDS is effective only for the low-frequency spectrum.

Techniques for High-Resolution and High-Speed ADCs

Considering typical requirements, three representative ADC architectures are compared in Table 58.1. To date, all techniques known to improve ADC resolution are as follows: trimming, dynamic matching, ratio- independent technique, capacitor-error averaging, walking reference, and self-calibration. However, the trimming is irreversible and expensive. It is only possible at the factory or with precision equipments. The dynamic matching technique is effective, but it generates high-frequency noise. The ratio-independent techniques either require many clock cycles or are limited to improve differential linearity. The latter case is good for monotonicity, but it also requires accurate comparison. The capacitor-error averaging technique requires three clock cycles, and the walking reference is sensitive to clock sampling error. The self-calibration technique requires extra hardware for calibration and digital storage, but its compatibility with existing proven architectures may provide potential solutions both for high resolution and for high speed.

The ADC self-calibration concepts originated from the direct code-mapping concept using memory. The calibration is to predistort the digital input to the DAC so that the DAC output can match the ideal level from the calibration equipment. Due to the precision equipment needed, this method has limited use. The first self-calibration concept applied to the binary-ratioed successive-approximation ADC is to internally measure capacitor DAC ratio errors using a resistor-string calibration DAC as shown in Figure 58.25 [15]. Later, an improved concept of the digital-domain calibration was developed for the multistep or pipeline ADCs [16].

The general concept of the digital-domain calibration is to measure code or bit errors, to store them in the memory, and to subtract them during the normal operation. The concept is explained in Figure 58.26 using a generalized N-bit MDAC with a capacitor array. If the DAC code increases by 1, the MDAC output should increase by Vref or Vref /2 with digital correction. Any deviation from this ideal step is defined as a segment error. Code errors are obtained by accumulating segment errors. This segment- error measurement needs two cycles. The first cycle is to measure the switch feedthrough error, and the next cycle is to measure the segment error. The segment error is simply measured as shown in Figure 58.26 using the LSB-side of the ADC by increasing the digital code by 1. In the case of N = 1, the segment error becomes a bit error. If binary bit errors are measured and stored, code errors should be calculated for subtraction during the normal operation. How to store DAC errors is a tradeoff issue. Examples of the digital calibration are well documented for the cases of segment-error [17] and bit-error [18] measurements, respectively.

The recent trend is to embed the error measurement cycles in the background. Compared to the foreground error measurement, the background technique can track any process variations over time and temperature. There are several ways to measure errors in background. An easiest way is either to retire a duplicate hardware for calibration or to steal cycles from normal cycles for calibration. A more elaborate way is to use a pseudo-random (PN) noise for calibration. The PN noise is a random pulse sequence of 1 and –1 with a zero mean. When calibrating the i-th stage, a known calibration voltage Vcal(i) is PN-modulated and injected into the i-th stage as shown in Figure 58.27. The injected Vcal(i) is quantized by the following ADC stages, and demodulated by the same PN sequence to generate the digital Vcal(i). The segment error can be obtained from this digitally measured Vcal(i) by comparing it to the ideal digital Vcal. The injected dither for calibration is a random noise spread in the Nyquist band, but it can be digitally subtracted. The only penalty is that the signal swing is reduced to accommodate a large dither added to the signal. For this reason, a fraction of Vref is used as Vcal.