High-Speed Circuit Design Principles:Delay Estimates

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Delay Estimates

The b1 coefficient (first-order estimate of TD) can now be found from the sum of the OCTCs.

High-Speed Circuit Design Principles-0021

First, however, we need to inspect the circuit to see whether there are any forward-path zeros in the network. These capacitors are identified by tracing the signal path from Vin to Vout. Two such capacitors can be seen in Figure 74.6(b). The CBC of Q1 passes the signal directly across what should be an inverting device, thus increasing delay. The CBE of Q2 reduces delay, passing the signal more quickly through the emitter follower stage. The a1 term can then be shown as in Ref. [8] to be

High-Speed Circuit Design Principles-0022

R2s will be calculated to illustrate the procedure. The remaining short-circuit equivalent resistances are shown in Table 74.2. Referring to Figure 74.8, the equivalent circuit for calculation of R1 is shown. This is the resistance seen across C2 when C1 is shorted. If C1 is shorted, V1 = 0 and the dependent current source is dead. It can be seen from inspection that

High-Speed Circuit Design Principles-0023

High-Speed Circuit Design Principles-0024

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