High-Speed Circuit Design Principles:Time Constant Methods in High-Speed Digital Design

Time Constant Methods in High-Speed Digital Design

The time constant methods described above are applicable to digital and analog designs. They are particularly useful in finding the dominant circuit elements that control bandwidth, delay, or risetime. This can give guidance in choosing bias currents, device areas, and passive circuit element values. The time constants also provide a window on device design, showing which internal device parameters need to be improved through design or process innovations. In this section, the time constant method will be used to estimate the delay of a static ECL frequency divider. This analysis will be used to compare two technologies used for high-speed static frequency divider implementation.

Evaluating Device Equivalent Circuit Model Elements for Time Constant Analysis The time constant analysis is only possible when equivalent circuit device model element values can be determined for computation. Digital circuit analysis requires determination of large-signal equivalents of these elements in most cases because the voltages and currents generally are varying over a wide range during the complete logic voltage or current swing. An ECL inverter, whose schematic is shown

in Figure 74.4, is selected for illustration because it is representative of many digital circuit problems. The analysis is based on work described in more detail in Ref. [8].

The first step is to construct the large-signal equivalent circuit model. The hybrid-pi bipolar junction transistor (BJT) model shown in Figure 74.5 has been used with several simplifications. The dynamic input resistance, rp, has been neglected because other circuit resistances are typically much smaller. The output resistance, ro, has also been neglected for the same reason. The collector- to-substrate capacitance, CCS has been neglected because in III–V technologies, semi-insulating substrates are typically used. The capacitance to substrate is quite small compared to other device capacitances. It may be necessary to include this in some silicon device implementations. Retained in the model are resistances Rbb, the extrinsic and intrinsic base resistance, and REX, the parasitic emitter resistance. Both are very critical for optimizing high-speed performance. Base–emitter junc- tion capacitance, Cbe, and diffusion capacitance, CD, are separated in this figure because they must be calculated independently.

Often CCB is split into two portions for more accurate modeling as seen in Figure 74.5. This split separates the intrinsic collector–base capacitance, CCBi, under the emitter from the extrinsic capacitance, CCBx, under the base contact region. The base resistance Rbb connects these two elements. Rather than calculating these through physical areas of the intrinsic and extrinsic base, the division of capacitance is better determined by best fitting the measured and modeled fmax.

Figure 74.6(a) is a schematic of the ECL inverter in Figure 74.4 where the half-circuit approximation has been used owing to the inherent symmetry of differential circuits [9]. In Figure 74.6(b), the equivalent circuit model has been inserted into the circuit in Figure 74.6(a). RIN is the sum of the driving

point resistance from the previous stage, probably an emitter follower output and Rbb1 of Q1. RL is the collector load resistor, whose value is determined by the single-ended output voltage swing, DV, and the DC emitter current, ICS . RL = DV /ICS . The REX of the emitter follower is included in REF . To simplify the example, the collector–base capacitances have been merged into single capacitors, C2 and C4 in Figure 74.6(b).

Now, calculate open-circuit resistances seen by each of the four capacitors in the circuit. C1 is the combined base–emitter diffusion and depletion capacitance of Q1. C2 is the collector–base depletion capacitance of Q1. C3 and C4 are the corresponding base–emitter and base–collector capacitances of Q2. Figure 74.7 represents the equivalent circuit schematic when C2 = C3 = C4 = 0. A test source, V1, is placed at the C1 location. R1o = V1/I1 is determined by circuit analysis to be

Table 74.1 shows the result of similar calculations for R2o, R3o, and R4o.

Considering the results in Table 74.1, it can be seen that there are many contributors to the time constants, and that it will be possible to determine the dominant terms after evaluating the model and circuit parameters. Next, estimates must be made of the device transconductances and capacitances to evaluate the time constant terms.