High-Speed Circuit Design Principles:Large-Signal Capacitances

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Large-Signal Capacitances

C1 and C3 of Figure 74.6(b) consist of the parallel combination of the depletion (space charge) layer capacitance, C be, and the diffusion capacitance, CD. The large-signal diffusion capacitance CD can be found from

High-Speed Circuit Design Principles-0019

where tf is the forward transit delay, tB + tC, as defined in Section 74.2. Note that this large-signal diffusion capacitance is reduced by the large-signal transconductance. The base requires charge to be delivered only while the collector current varies from 0 to ICS. This occurs within a VBE range of approxi- mately 2kT/q or 50 mV. The overall voltage swing DVLogic is much greater than 2kT/q, typically by factors of 2 or 3. While depletion capacitance must be charged during the entire logic swing, the diffusion capacitance charging occurs over a smaller subset of voltage. Thus, for devices with small transit times, the effect of CD on delay is generally much smaller than that of Cbe, the base–emitter depletion capacitance.

The diffusion capacitance can be larger in cases such as the emitter follower, Q2 of Figure 74.6(a), C3 of Figure 74.6(b), where the VBE varies over a relatively smaller range. In this instance, the small signal gm is appropriate for calculating CD.

The base–emitter depletion capacitances must also be added to C1 and C3. Also, C2 and C4 are the base–collector depletion capacitances. Depletion capacitances are voltage varying according to

High-Speed Circuit Design Principles-0020

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