High-Speed Circuit Design Principles:Technology-Independent Design Methodologies

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Technology-Independent Design Methodologies

Zeroth-Order Delay Estimate

The first technique, useful for some digital circuit applications, uses the simple relationship between voltage and current in a capacitor

High-Speed Circuit Design Principles-0000

This equation is relevant when circuit performance is dominated by wiring or fanout capacitance. This will be the case if the delay predicted by this equation caused by the total loading capacitance, CL, significantly exceeds the intrinsic delay of a basic inverter or logic gate. To apply this approach, determine the average current available from the driving logic circuit for charging (ILH) and discharging (IHL) the load capacitance. The logic swing DV is known, so low-to-high (tPLH) and high-to-low (tPHL) propagation delays can be determined from Eq. (74.1). These delays represent the time required to charge or discharge the circuit output to 50% of its final value. Thus, tPLH is given by

High-Speed Circuit Design Principles-0001

At this limit, where speed is dominated by the ability to drive load capacitance, we see that increasing the currents will reduce tP . In fact, the product of power (proportional to current) and delay (inversely proportional to current) is nearly constant under this situation. Increases in power lead to reduction of delay until the interconnect distributed RC delays or electromagnetic propagation delays become comparable to tP . The equation also shows that the small voltage swing DV is good for speed if the noise margin and drive current are not compromised. This means that the devices with high transconductance are faster in such applications.

This method can be effective in estimating delays in large digital ICs where wiring capacitance is dominant. In the case of deeply scaled submicron circuits, distributed RC delay on interconnect lines must also be considered. Because the emphasis in this chapter is on small, very high-speed circuits, other methods that are more dependent on device parasitics and intrinsic delays will be developed next. There are many references that give more information on the simple delay estimation methods [1].

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