An Exploration of Hardware Architectures for Face Detection:Neural Network Hardware Face Detection

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Neural Network Hardware Face Detection

In this section, we present the implementation of a face detection algorithm based on the classification- based neural network algorithm proposed originally by Rowley et al. [8]. The algorithm provides high parallelism capabilities for hardware implementation, and achieves high detection rates when trained extensively. To illustrate however the challenges in a hardware implementation, we show how the targeted hardware platform can affect the implementation. As such, we present two different design approaches; the first targets an ASIC implementation, whereas the second targets an FPGA implementation.

The neural network algorithm consists of the three stages outlined in Section 83.2.1. The first stage is the IPG stage, and scans the image at different scales generating 20 × 20 search windows as shown in Figure 83.2 (right). A search window is defined as an image subregion searched for a human face. Each of the windows is treated as an individual image. The windows are then passed through an IE stage where histogram equalization and lighting correction is performed. Finally, the 20 × 20 window is evaluated for a face or not using three separate neural networks, each of which looks at the image in a different manner as shown in Figure 83.2. The first network looks at 4 10 × 10 regions, the second looks at sixteen 4 × 4 regions, and the third looks at six horizontal 5 × 20 overlapping strips. Note that the neural network structure can change to adapt to different image sizes [14], at the cost of a larger network size. General purpose neural network processors such as the ones proposed in Refs. [23,24] can be used to map neural networks which change in connectivity and size.

The hardware implementation can be partitioned into three stages, each stage designed individually and interfaced to each other. The implementation of the detection stage, however, is the one that we place more emphasis on, and in this section we illustrate its implementation when targeting different hardware platforms. We first address the design of an ASIC, which performs face detection and consists of all the three stages.

An Exploration of Hardware Architectures for Face Detection-0135

An Exploration of Hardware Architectures for Face Detection-0136

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