Silicon-on-Insulator Technology:SOI Challenges

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SOI Challenges

Although SOI is already a mature technology, there are still serious challenges in various domains: fundamental and device physics, technology, device modeling, and circuit design. For example, quantum transport phenomena play an increasing role in ultrathin SOI transistors. It is clear that new physical concepts, ideas, and modeling tools are needed to account for minimum-size mechanisms and to take advantage of them. As far as the technology is concerned, a primary challenge is the fabrication of SOI wafers with ultrathin film, thin BOX, excellent thickness uniformity, low defect content, and reasonable cost.

There is a demand for appropriate characterization techniques, either imported from other semi- conductors or entirely conceived for SOI [1]. Such a pure SOI technique is the pseudo-MOS transistor (Ψ–MOSFET, Fig. 3.13) [58]. Ironically, it behaves very much like the MOS device that Shockley attempted to demonstrate 60 years ago but, at that time, he did not have the chance to know about SOI. The inset of Figure 3.13 shows that the Si substrate is biased as a gate and induces a conduction channel (inversion or accumulation) at the film–oxide interface. Source and drain probes are used to measure ID(VG) characteristics. The Ψ–MOSFET does not require any processing, hence valuable information is

Silicon-on-Insulator Technology-0052

directly available: quality of the film, interface and oxide, electron/hole mobilities, and lifetime. Contact- less optical probing in Ψ–MOSFET configuration would be attractive.

Full CMOS processing must address typical SOI requirements such as the series resistance reduction in ultrathin MOSFETs (via local body oxidation, elevated source and drain structures, etc.), the lowering of the source–body barrier by source engineering (silicidation, SiGe, etc.), the control of the parasitic bipolar transistor, and the limitation of self-heating effects. It is now clear that the best of SOI is certainly not achievable by simply using a very good bulk-Si technology. For example, DG SOI MOSFETs deserve special processing and design.

According to process engineers and circuit designers, PD SOI MOSFETs are more user friendly as they maintain the flavor of bulk-Si technology. In contrast, very thin FD transistors show superior tolerance to short-channel effects. A possible solution is the incorporation of a GP in the BOX.

Advanced physics-based and compact modeling is requested for correct transcription of the transistor behavior, including the transient effects owing to body charging and discharging, floating body mechanisms, bipolar transistor, dual-gate operation, quantum effects, self-heating, and short-channel limitations.

It is obvious that SOI does need SOI-dedicated CAD libraries. This implies a substantial amount of work which, in turn, will guarantee that the advantages and peculiar constraints of SOI devices are properly accounted for. The optimum configuration of memories, microprocessors, DSP, etc. are different in SOI as compared with bulk. Not only can SOI afford to combine FD/PD, low/high power, and DT–MOSFETs into a single chip, but also the basic mechanisms of operation differ.

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