Silicon-on-Insulator Technology:SOI Devices CMOS Circuits

By -
SOI Devices
CMOS Circuits

High-performance SOI CMOS circuits, compatible with low-power or high-speed ULSI applications have been repeatedly demonstrated on deep submicron devices. High-end microprocessors are being fabricated on SOI by IBM, AMD, Motorola, etc. RF SOI devices also show unchallenged capability in terms of frequency and noise. Extremely low-power circuits for mobile communication, portable processors operated with one-battery supply (0.5 to 1.2 V), and even battery-less watches are currently fabricated on SOI Unibond wafers. The SOI versatility has been taken advantage of for conceiving capacitor-less DRAMs.

SOI is also an ideal substrate for systems-on-chip. FD CMOS SOI circuits operate successfully at temperatures beyond 300°C (for aeronautics and automobiles): the leakage currents are much smaller and the threshold voltage is less temperature sensitive (»0.5 mV/°C) than in bulk Si [9]. In addition, many SOI circuits are radiation-hard, able to sustain doses above 10 Mrad, for the space industry.

Bipolar Transistors

As a consequence of the small film thickness, most of the bipolar transistors have lateral configuration. The implementation of BiCMOS technology on SOI has resulted in devices with high cutoff frequency. Hybrid MOS-bipolar transistors with increased current drive and transconductance are formed by con- necting the gate to the floating body (or base): the MOSFET action governs in strong inversion whereas, in weak inversion, the bipolar current prevails [10].

Vertical bipolar transistors have been processed in thick-film SOI (wafer bonding or epitaxial growth over SIMOX). An elegant solution for thin-film SOI is to replace the buried collector by an inversion layer activated by the back gate [10].

High-Voltage Devices

The outstanding advantage is the dielectric isolation. Power transistors can have lateral (LD–MOSFETs essentially for lightening) or vertical architecture. Lateral double–diffused MOSFETs (LDMOS), with long drift region, were fabricated on SIMOX and showed 90 V–1.3 A capability [11]. Vertical power devices (IGBT, LDMOS, VMOS, etc.) can be accommodated in a thicker wafer-bonding SOI.

SOI offers the possibility to synthesize locally a BOX (SON process or “interrupted” SIMOX, Fig. 3.2b5). Therefore, a vertical power transistor, located in the bulk region of the wafer, can be controlled and rendered “smart” by being located next to a low-power SOI CMOS [12] (Fig. 3.3a). A variant of this concept is the “mezzanine” structure, which served for the fabrication of a 600 V/25 A smart-power

Silicon-on-Insulator Technology-0038

device [13]. Double SIMOX (Fig. 3.2b3) has also been used to combine a power MOSFET, with a double- shielded high-voltage lateral CMOS and an intelligent low-voltage CMOS circuit [12].

Innovative Devices

Most innovative devices make use of special SOI features such as the adjustment of the thickness of the Si overlay and BOX, and the implementation of additional layers underneath the BOX (Fig. 3.3b).

SOI is an ideal material for microsensors and MEMS because the Si/BOX interface gives a perfect etch- stop mark, making it possible to fabricate very thin membranes (Fig. 3.3c). Transducers for detection of pressure, acceleration (air bags), gas flow, temperature, radiation, magnetic field, etc. have successfully been integrated on SOI [1,13].

Three-dimensional circuits containing consecutive thin silicon and BOX layers have been demonstrated with the ELO and ZMR methods. For example, an image-signal processor is organized in three levels: photodiode arrays in the upper SOI layer, fast A/D converters in the intermediate SOI layer, and arithmetic units and shift registers in the bottom bulk Si level [14].

The gate all–around (GAA) transistor of Figure 3.3d, based on the concept of volume inversion, is fabricated by etching a cavity into the BOX and wrapping the oxidized transistor body into a poly-Si gate [10]. The family of SOI devices also includes optical waveguides and modulators, microwave transistors integrated on high-resistivity SIMOX, twin-gate MOSFETs, and other exotic devices [1,10]. They do not belong to science fiction: the devices have already been demonstrated in terms of technology and functionality . . . even if most people still do not believe that they can operate indeed.

Finally, most of the Si nanoelectronic devices (SET, tunneling transistors, quantum dots and wires) have used SOI, either for the ease of processing or for ultrathin film capability [15,16].

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more