Silicon-on-Insulator Technology:Small-Geometry Effects

Small-Geometry Effects

Parasitic Bipolar Transistor

In both FD and PD MOSFETs with submicron length, the source–body junction can easily be turned on. The inherent activation of the lateral bipolar transistor has favorable (extra current flow in the body) or detrimental (premature breakdown, Fig. 3.5e) consequences.

The breakdown voltage is evaluated near the threshold, where the bipolar action prevails. The break- down voltage is especially lowered for n-channels, shorter devices, thinner films, and higher temperatures. As expected, the impact ionization rate and related floating-body effects are attenuated at high temper- ature. However, the bipolar gain increases dramatically with temperature and accentuates the bipolar action: lower breakdown and latch voltages [9].

Typical Short-Channel Effects

Familiar short-channel effects are the threshold voltage roll-off (Fig. 3.7a), and subthreshold swing degradation owing to charge sharing between the gate and source and drain terminals. Note also that in very short FD MOSFETs, the lateral profile of the back-interface potential can be highly inhomogeneous; this leads to interface coupling effects that are not equal in the middle of the channel and at the proximity of source/drain regions.

The major short-channel effect in SOI is due to the penetration of the electric field from the drain into the BOX and substrate (Fig. 3.7b, inset). The fringing field increases the surface potential at the film–BOX interface: drain-induced virtual substrate biasing (DIVSB) [29,30]. Since the front and back interfaces are naturally coupled in FD films, the front-channel properties become degraded. In particular, the threshold voltage VT is lowered with increasing drain bias, very much as in drain-induced barrier lowering (DIBL), although DIVSB is totally distinct.

The key parameters in SOI are the doping level, film thickness, and BOX thickness [31]. Ultrathin, FD MOSFETs show improved performance in terms of VT roll-off, DIBL, and DIVSB, as compared with PD SOI or bulk Si transistors (Fig. 3.7) [32]. The worst case occurs when the film thickness corresponds to the transition between full and partial depletion.

(b) Threshold voltage lowering DVT /DVD by DIBL and DIVSB effects versus film thickness and channel doping; the doping effect is cancelled for films thinner than 15 nm (channel length L = 0.1 mm).

The transconductance is obviously improved in deep submicron transistors. Velocity saturation occurs as in bulk silicon. The main short-channel limitation of the transconductance comes from series resistance effects.

The lifetime of submicron MOSFETs is affected by hot-carrier injection into the gate oxide(s). The degradation mechanisms are more complex in SOI than in bulk Si, owing to the presence of two oxides, two channels, and related coupling mechanisms [33]. The defects are created at the interface where the carriers flow or at the opposite interface. As a guideline, SOI n–MOSFETs degrade less than bulk Si MOSFETs for VG = VD /2 (i.e., for maximum substrate current) and more for VG = VT (i.e., enhanced hole injection). The device aging is accelerated by accumulating the back interface [33].

Scaling Issues

The scaling strategy in SOI is illustrated in Figure 3.7b. The threshold voltage lowering with drain bias (by DIVSB and DIBL) is compared for highly doped and undoped MOSFETs. A thick undoped film is definitely not suitable. However, film thinning gradually erases the advantage of heavy doping. For 15 nm thick film, DVT becomes reasonable and the doping effect disappears. It is concluded that undoped and ultrathin MOSFETs benefit from an unchallenged electrostatic control and are exception- ally robust to short-channel effects. Other advantages are the high carrier mobility and excellent subthreshold slope.

Further solutions for short channels aim at reducing the fringing field penetration in the BOX and substrate: thinner BOX with lower permittivity, double-gate structure, or ground plane (highly doped region or metal layer underneath the BOX) [30,34].

By solving the Poisson equation, it is demonstrated that the minimum channel length is proportional to the film thickness: Lmin = 4tsi [35]. This guiding rule makes it clear that SOI MOSFETs will break the 10-nm-length barrier as soon as films thinner than 3 nm will be routinely manufactured [36]. As a confirmation, 2.5-nm-long transistors with acceptable characteristics have been simulated for 1-nm-thick SOI films [37]. On the practical side, 6-nm-long SOI MOSFET [38] as well as film thinning down to a few monolayers (1 nm) [39] have been achieved already.

It is worth noting that emerging CMOS technologies such as strained-Si, SiGe, and Ge do not compete with SOI. They must be SOI-like: whatever the semiconductor, the electrostatic problems are more or less the same. The semiconductor film should be ultrathin and placed on an insulator. Otherwise, the short-channel effects will become an issue again in extremely small MOSFETs.

Ultrathin Channel Effects

The ultrathin body, needed for ultimate scaling, enables very interesting thickness effects. Not only is the interface coupling amplified, but also supercoupling may occur [22,40]. Supercoupling reflects the fact that the film tends to behave as a quasi-rectangular well: when the potential at one interface is modified by the gate, the potential of the entire film follows. The notion of front and back channels becomes obsolete and needs to be replaced by the concept of volume inversion [21,1] or volume accumulation. Since the front and back channels cannot be separated, formulations like “front-channel mobility” should be translated into “mobility seen from the front gate.”

In sub-10-nm-thick films, vertical quantum confinement and subband splitting become noticeable, increasing the threshold voltage. Monte Carlo simulations suggest that the carrier mobility is maximum in 3–5-nm-thick films [41]. However, there is no experimental support to date. Early measurements actually indicated the opposite trend, i.e., a mobility degradation in thinner films.

Figure 3.8 shows that in long, 10–20-nm-thick MOSFETs the thickness effect is irrelevant, whereas in short-channel transistors the mobility seems to decrease for thinner films. This difference implies that the apparent mobility degradation in thinner films is merely a series-resistance effect [42]. Other char- acterization artifacts have been identified (GIFBE, poly depletion, etc.).

Self-Heating and Alternative BOX Layers

Self-heating, induced by the power dissipation, is exacerbated in SOI by the poor thermal conductivity of the surrounding SiO2 layers. Self-heating is responsible for mobility degradation, threshold voltage shift, and negative differential conductance shown in Figure 3.5f. The temperature raise can exceed 100 to 150°C in SOI [43]. Thin BOXs (<100 nm) and thicker Si films (>100 nm) are suitable when self- heating becomes a major issue.

A more revolutionary solution is to modify the generic SOI structure by replacing the standard SiO2 BOX with Al2O3, AlN, SiC, diamond, quartz, etc. (Fig. 3.9a) [44]. These new structures are still SOI, except that the letter I is no longer restricted to SiO2 and recovers the general meaning of buried insulator. Reducing the self-heating by 50°C represents an immediate gain of more than 25% in mobility (µ ~ T–1.5). This improvement applies simultaneously to electrons and holes and corresponds to the gain in speed expected from the “next” CMOS generation. It follows that the carrier mobility can be engineered not only by using strained silicon and various crystal orientations (<100> and <110>), but also by preventing excessive self-heating. These novel dielectrics are even more attractive for

temperature management in high-power SOI devices and for photonic applications.

A subsequent problem is that the change in the dielectric constant impedes on the 2D distributions of the electric potential in the transistor [44,45]. The classical short-channel effects (charge sharing and DIBL) are marginally degraded for high-K BOX. A 25-nm-long, alumina-BOX MOSFET exhibits only a 25% larger threshold voltage roll-off, which can be further attenuated by thinning the BOX [45]. The control of the fringing fields (DIVSB) is excellent (∆VT/VD = 100 mV/V) for diamond, quartz, SiO2, and air or modest (250 mV/V) for SiC and Al2O3. In the latter case, the device architecture can be optimized by including a ground plane (GP).

Figure 3.9b shows combined solutions: ultrathin Si film (5 to 10 nm), thin BOX (50 nm), and GP. Without GP, DIVSB effect increases exponentially in MOSFETs shorter than 50 nm. A GP is more effective for shorter channels and alumina BOX. The conclusion is twofold: the slight electrostatic disadvantage of alumina BOX is practically erased in GP MOSFETs, and it is minor compared with the huge thermal advantage.