Power IC Technologies:Intelligent Power IC

Introduction

VLSI technology has advanced so rapidly that gigabit DRAMs have been realized, and the technology faces silicon material limit. Microelectronics mostly advances signal-processing LSIs such as memories and microprocessors. Power systems and the related circuits cannot be outside the influence of VLSI technology [l]. It would be quite strange for power systems alone to still continue to consume a large space while brains become smaller and smaller. In contrast, almost all of the systems require actuators or power devices to control motors, displays, and multimedia equipment. The advance in microelectronics made it possible to integrate large-scale circuits in a small silicon chip, ending up in high system performance and resultant system miniaturization. The system miniaturization inevitably necessitated power IC development. Typical early-developed power ICs were audio power amplifiers, which used bipolar transistors as output devices. pn junction isolation method was well suited to integrate bipolar transistors with control circuits.

Real advancements in intelligent power ICs were triggered by the invention of power DMOSFETs [2] in the 1970s. DMOS transistors have ideal features for output devices of power ICs. No driving DC current is necessary, and large current can be controlled simply by changing the gate voltage. In addition, DMOS switching speed is sufficiently fast.

The on-resistance of vertical DMOSFET has been greatly reduced year after year with the advance in fine lithography in LSI technology. In the mid-1980s, the new concept of Smart Power [3] was introduced. Smart Power integrates bipolar and CMOS devices with vertical DMOS, using a process primarily optimized for polysilicon gate self-aligned DMOS. The main objective is to integrate control and pro- tection circuits with vertical power devices not only to increase device reliability and performance but also to realize easy use of power devices. The concept Smart Power was applied to high-voltage vertical DMOS with drain contact on the backside of the chip because discrete DMOS technology was already well advanced in the early 1980s. Their main application field was the automotive, replacing mechanical relays and eliminating wire harness.

As the technology of microlithography has further advanced, the on-resistance of DMOS, especially low-voltage DMOS, has continuously decreased. In the early 1990s, the on-resistance of low-voltage lateral DMOS became lower than that of bipolar Trs [4]. It was even true that low-voltage lateral DMOS is superior to vertical planar discrete DMOS since fine lithography does not contribute to decrease in on-resistance of vertical DMOS because of the parasitic JFET resistance. Recently, with the introduction of a 0.6 µm design rule, lateral DMOS has become predominant over the wide voltage range from 20 up to 150 V. Mixed technology, called BCD [4], integrating BiCMOS and DMOS, is now widely accepted for low-voltage power ICs.

For high-voltage power ICs, DMOS is not suitable for output devices because of a high on-resistance. Thyristor-like devices, such as GTOs have conventionally been used for high-voltage applications. Inte- gration of thyristor-like devices needs a method of dielectric device isolation (DI). The conventional DI method, called EPIC [5], has been used for high-voltage telecommunication ICs, called SLIC. However, it has problems of high cost and large wafer warpage. In 1985 and 1986, wafer direct-bonding technology was invented [6], and low-cost DI wafers became available. In 1990, it was shown [7] that a high-voltage of 500 V can be realized even in relatively thin SOI by applying a large part of the voltage across the buried oxide. Thin SOI layer can be easily isolated by trenches. This opened up the new field of high- voltage SOI technology. Wafer warpage of directly bonded SOI wafers is very small. This made it possible not only to fabricate large diameter (8 in) SOI wafers but also to apply advanced lithography to SOI power ICs. The chip size of SOI power ICs can be reduced by narrow trench isolation and by use of high- performance lateral IGBTs. The low-cost DI wafers and the chip size reduction have widened the appli- cation fields of SOI power ICs, covering the applications of automotive, motor control, and PDP drivers.

Intelligent Power IC

Figure 7.1 shows typical functions integrated into intelligent power ICs. The most important feature of the intelligent power IC is that a large power can be controlled by logic-level input signals and all the cumbersome circuits such as driving circuits, sense circuits, and protection circuits required for power device control are inside the power ICs.

Technologies for realizing such power ICs are classified into three categories, as shown in Figures 7.2–7.4. These are self isolation, junction isolation, and dielectric isolation. Self isolation is a method that does not use any special means to isolate each device and each device structure automatically isolates itself from the other.

Junction isolation (JI) is a method that uses reverse-biased junction-depletion layers to isolate each device. JI is the most frequently used method for low-voltage power ICs, using bipolar transistor or DMOS outputs.

Junction isolation is not sufficient to isolate IGBTs or thyristors. Dielectric isolation is a method that uses silicon dioxide film to isolate devices and, thus, offers complete device isolation. Although the EPIC method has conventionally been used, the high cost of wafer fabrication has been a problem. Recently, wafer direct-bonding technology has been invented and bonded SOI wafers are available in a lower price.

pn Junction Isolation

pn junction isolation is the most familiar method and has been used since the beginning of the bipolar IC history. Figure 7.5 shows the cross section of a typical junction isolation structure. First, an n-type epitaxial layer is formed on p-type silicon substrate. p-type diffusion layers are then formed to reach

p-type substrate, resulting in isolated n-type islands surrounded by p-type regions. By keeping the substrate potential in the lowest level, the pn junctions, surrounding the islands, are reverse-biased and the depletion layers are formed to electrically isolate each island from the others.

pn junction isolation is particularly useful for low-voltage power ICs, called BCD technology. BiCMOS circuits and LDMOS devices are integrated in a single chip in BCD technology as seen in Figure 7.3.

If this method is applied to high-voltage power ICs, a thick n-type epitaxial layer is required and deep isolation diffusions are necessary. Deep diffusion accompanies large lateral diffusion, ending up in large isolation area. One solution for this is to use buried p+ diffusion layers for upward isolation diffusions as shown in Figure 7.6. However, 200 V is a practical limit for the conventional pn junction isolation.

A variety of method was proposed to overcome this voltage limit. Figure 7.7 shows a typical example for this [8]. A shallow hole is formed where a high-voltage device is formed before the n-type epitaxial growth. This allows a locally thicker n-type epitaxial layer for high-voltage transistors.

Another distinguished example is shown in Figure 7.8, where n+ substrate is used in place of p-type substrate. p- and n-type epitaxial layers are subsequently formed. This example makes it possible to integrate a vertical DMOSFET with a backside drain contact with junction-isolated BiCMOS control circuits. This structure was proposed as Smart Power in the mid-1980s.

BCD Power ICs and Technology Road Map

Figure 7.9 shows the technology road map for BCD power ICs. Before 1995, power ICs fabrication technology was about 10 years behind that of CMOS. Since 1996, the design rule of power ICs has been rapidly approaching

that of CMOS. There are two main reasons. First, lower-voltage LDMOS becomes more important for the application of mobile equipments, such as cell phones. The on-resistance of the low-voltage LDMOS improves significantly by adopting finer design rule as shown in Figure 7.10. The detailed explanation of LDMOS is presented in Section 7.6. The other is the need of system integration. More functionality needs to be integrated to reduce the size of the system. This is especially true in mobile equipments and automotive applications.

Impact of Dielectric Isolation

Dielectric isolation (Dl) is a superior method for integrating any kind of devices in a single chip. DI has many advantages [9,10] over junction-isolation techniques with regard to the points wherein:

1. Virtually all integrated components can be treated as if they were discrete devices, so that circuit design becomes easy

2. Bipolar devices, including thyristors can be integrated without any difficulties

3. Coupling between two devices can be minimized, thus attaining better IC performances: no latch- up, high-speed, large noise immunity, and ruggedness

4. High-temperature operation is feasible because there are virtually no parasitics and leakage current is low

5. Radiation hardness for space use

Figure 7.11 shows a cross section of conventional DI, called EPIC. The crystalline silicon islands, com- pletely surrounded by silicon dioxide film, were floating in the supporting substrate made of thick polysilicon layer. The fabrication process of the EPIC wafers is complicated and is illustrated in Figure 7.12. The problem of EPIC is high cost of wafers and large wafer warpage. The development of EPIC method was initiated by the early works of McWilliams et al. [11], Lathrop et al. [12], and Bouchard et al. [13] in 1964. EPIC method was first applied to high-speed bipolar ICs owing to low parasitic capacitance.

Early work on high-voltage integrated circuits was triggered by the need for display drivers and high- voltage telecommunication circuits. Efforts to achieve high-voltage lateral MOSFETs started in the early 1970s and 800 V lateral MOSFET using RESURF concept and DMOS (DSA [2]) technology was developed for display drivers in 1976, before the RESURF concept was fully established [14].

The need for high-voltage SLICs advanced the EPIC technology because it required electrically floating high-voltage bidirectional switches, which were realized only by the DI technique.

A variety of dielectric isolation methods, classified as silicon on insulator (SOI) technology, were invented in the 1970s. These are silicon on sapphire (SOS) [15], SIMOX [16], and recrystallized polysilicon such as ZMR [17]. Silicon wafer direct-bonding (SDB) [6] was proposed in 1985.

The major fabrication methods are SIMOX and wafer bonding. SIMOX is a method that forms a buried oxide layer by a high dose of oxygen ion implantation and subsequent high-temperature annealing. Wafer bonding is a method which bonds an oxidized wafer and a substrate wafer in room temperature and strengthens the bond by annealing at high temperature. The thickness of the bonded SOI layer is adjusted by mechanical grinding and polishing.

In the late 1980s, the MOS gate power device technology has been greatly improved. Especially, the success in the MOS bipolar composite devices such as IGBTs [18,19] and MCTs [20] made it possible to control a large current by the MOS gate. The large current-handling capability of the MOS gate bipolar devices has accelerated adopting DI with IGBT outputs and even MOS gate thyristors in power ICs.

In the early developed SLICs, double-injection devices with current control gates such as gated diodes and GTOs were used as high-voltage switches [21]. Recently developed new version SLIC (telecommunication ICs) have adopted lateral IGBTs or MOS-gated thyristors because of the ease of gate drive. All the commercialized SLICs, so far, adopted the conventional DI method. The success in SLIC was supported by the fact that monolithic integration and added function deserved the expensive Dl for telecommunication application.

In the 1990s, a low-cost DI method realized by SOI technology, using several micron thick or less silicon layers, changed the situation of DI research and widened the application fields. If the silicon layer is thin, devices in the SOI layer are isolated with narrow trenches. This makes SOI technology very attractive for high-voltage applications. The high-voltage SOI research work started in the early 1990s [1,7]. The research works have been directed toward:

1. Monolithic device integration of multiple number of high-voltage–high-current devices with control circuits

2. ICs allowing high-temperature operation and ruggedness

3. Low-cost Dl power IC process development

4. High-current high-speed MOS-controlled lateral output devices with self-protection functions