Power IC Technologies:High-Voltage SOI Technology

High-Voltage SOI Technology

SOI power ICs are classified into two categories from the viewpoint of SOI wafer structure. The difference is whether there is a buried n+ layer on the buried oxide. Figure 7.16 shows a typical device structure, employing an n+ buried layer on the buried oxide. The breakdown voltage is determined with the thickness of the high-resistivity n layer or the thickness of the depletion layer. The maximum breakdown voltage is limited to below 100 V because of SOI layer thickness or practically available trench depth. For this case, SOI wafers are used as a simple replacement for conventional DI wafers.

Figure 7.17 shows another typical SOI power IC structure, employing a high-voltage lateral IGBT. n– drift layer is fully depleted by the application of a high-voltage. As the buried oxide and the depletion layer both share the applied voltage, high breakdown voltage is realized in relatively thin SOI [7]. This type of power ICs fully enjoy the features of SOI technology and is described in detail in this section.

There are two big challenges associated with high-voltage devices on SOI. One is how to realize a high breakdown voltage under the influence of substrate ground potential. The other is how to attain a low on-resistance device in the thin silicon layer. In the conventional Dl, the wrap-around n+ region (see Figure 7.16) is used in the DI island to prevent the influence of substrate potential on the device breakdown voltage. However, for thin SOI layers, this method cannot be used. The bottom silicon dioxide layer simply works as an undoped layer as far as Poisson equation is concerned. Thus, a SOI layer on a grounded silicon substrate structure behaves in a way similar to the structure of a doped n-type thin silicon layer on undoped silicon layer (corresponding to silicon dioxide) on grounded p silicon substrate. Thus, the SOI layer works in the same way as a Resurf layer.

A high breakdown voltage of a SOI layer device can be realized by applying a large part of the voltage across the buried dioxide film. The buried oxide film is able to sustain a large share of the applied voltage, because the dielectric breakdown field is larger than that of silicon.

Figure 7.18 shows typical SOI diode structure and its electric potential distribution. It is seen that almost a half of the voltage is applied across the buried oxide. Figure 7.19 shows the electric field distribution along the symmetry axis of the diode of Figure 7.18. The electric field in the oxide is larger than that in silicon. This is because the two electric field components, Et(Si) and Et(I), normal to the interface of the silicon and the bottom insulator layer, have the relation

where ε(Si) and ε(I) denote dielectric constants for silicon and silicon dioxide, respectively. Using an insulator film with a lower dielectric constant will increase the device breakdown voltage because the insulator layer sustains a larger share of the applied voltage.

SOI Resurf

The breakdown voltage in SOI diodes is determined in the way similar to Resurf devices. The SOI structure can be regarded as n-epilayer/undoped silicon layer/p+ silicon layer. Figure 7.20 shows the breakdown voltage of SOI diode as a function of epilayer dose with buried oxide thickness as a parameter. There is an optimum epilayer dose for the high breakdown voltage in SOI devices.

If the SOI diodes is optimized in lateral direction, the breakdown voltage is substantially limited to the breakdown voltage of the 1-D MOS diode portion as illustrated in Figure 7.21, consisting of n+/n–/ oxide/substrate. Figure 7.22 shows the measured SOI device breakdown voltage as a function of SOI layer

thickness with buried oxide thickness as a parameter. The calculated breakdown voltage of 1-D MOS diodes are shown together. A 500 V breakdown voltage can be obtained with a 13-µm-thick SOI with 3-µm-thick buried oxide.

It is very difficult to achieve a high breakdown voltage exceeding 600 V in a simple SOI structure, because a thicker buried oxide layer of 4 µm or more is required. The maximum breakdown voltage is substantially limited to the breakdown voltage of the 1-D MOS diode and the actually realized breakdown voltage is lower than this limit. If the influence of the substrate potential can be shielded, it is possible to achieve a higher breakdown voltage in the SOI device.

A new high-voltage SOI device structure, which is free from the above constraints, was proposed in 1991 [1], which realizes 1200 V breakdown voltage even with a thin buried oxide [23].

To improve the breakdown voltage, an SOI structure with shallow n+ layer diffused from the bottom of SOI layer was proposed [24]. Figure 7.23 shows the structure of an SOI diode with shallow n+ layer and the electric field strength in the MOS diode portion. The figure also shows the electric field for the structure without shallow n+ layer. In general, if a larger proportion of the applied voltage is sustained by the bottom oxide layer, a higher breakdown voltage can be achieved. The problem is how to apply higher electric field across the buried oxide without increasing the electric field strength in the SOI layer. This problem can be solved by placing a certain amount of positive charge on the SOI layer–buried oxide interface. The positive charge in the interface shields the high electric field in the buried oxide, so that a voltage across the oxide layer can be increased without applying higher electric field in the SOI layer. The shallow n+ layer diffused from the bottom is a practical technique to place the positive charge on the SOI layer–buried oxide interface as shown in Figure 7.23. The required dose of the shallow n+ layer is around 1 × 1012 cm–2.

Very Thin SOI

Merchant et al. [25] showed that the SOI diode breakdown voltage is significantly enhanced if the SOI layer thickness is very thin, e.g., such as thin as 0.1 µm. As shown in Figure 7.22, reduction of the SOI layer thickness enhanced the breakdown voltage if the thickness is less than 1 µm. This is because the carrier path along the vertical high electric field is as short as the SOI layer thickness, so that the carriers reach the top or bottom surface of the SOI layer before ionizing sufficient amount of carriers for avalanche multiplication along the path. They proposed combination of the very thin SOI layer and a linearly graded impurity profile of the n-type silicon layer for a high-voltage n+n–p+ lateral diode. A breakdown voltage of 700 V was realized by this structure.

The exact 2-D simulations revealed that the ideal profile for a lateral diode is approximated by a function which is similar to a tangent function, as shown in Figure 7.24. The important point is that the p layer impurity profile should also be graded and that the linearly graded portion is terminated by the exponentially increasing ending portions. By using the proposed profile, a 5000 V lateral diode was

predicted to be realized on 0.1 µm SOI on a 600-µm thick quartz substrate. A completely uniform lateral electric field is realized at 5000 V (see Figure 7.24).