Power IC Technologies:Examples of High-Voltage SOI Power IC

Examples of High-Voltage SOI Power IC

The current main applications of high-voltage SOI power ICs are DC motor control and flat panel display drivers. Recently, technologies for color plasma display panels have been greatly improved, and demands for PDP driver ICs have increased. There are several reports [32,33] on the development of such ICs using SOI wafers. Flat panel display drivers have to integrate a large number of high-voltage devices. Trench isolation and LIGBTs are key techniques for reducing chip size and resultant cost.

Another large market is the motor control field. Home-use appliances use a number of small motors, which are directly controlled by a AC source line. Single-chip inverter ICs are able to reduce system sizes and increase system performance. Figure 7.40 shows a 500 V 1 A single-chip inverter IC [34] for DC brushless motors. It integrates six 500 V 1 A LIGBTs, six 500 V diodes, control protection, and logic circuits. Figure 7.41 shows a block diagram of the fabricated inverter ICs. The bootstrapping technique is adopted as the internal high-side voltage source. The circuits include high-voltage lateral IGBTs, free- wheeling diodes, gate drive circuits for LIGBTs, bootstrap diode, logic circuits controlling the rotor of a DC motor, PWM circuit, and various protection circuits. The protection circuits, which improve the system reliability, are undervoltage protection circuit monitoring the internal high-voltage source and external voltage source, over-current protection circuit, and overheating protection circuit.

There are two process options for high-voltage SOI power ICs. These are (1) BiCMOS/DMOS control circuits or (2) only CMOS/DMOS circuits. The latter CDMOS process without bipolar transistors is suitable for high-voltage SOI power ICs, because bipolar devices often cause malfunction of the analog circuits in the high-side driver. For example, Figure 7.42a and Figure 7.42b show how the dV/dt current

flows and causes malfunction of lateral pnp transistors, if the pnp transistors are used in the high-side driver circuit. Figure 7.42a shows the depletion layer formation when the voltage between the base and the emitter is zero and the pnp is off-state. When the low-side output LIGBT is turned-off, the ground level of the whole high-side driver circuits is elevated and the depletion layer is initially created from the buried oxide. After the depletion layer reaches the other depletion layer around the p+ collector layer, holes are injected and an inversion layer is created on the buried oxide in Figure 7.42b. Although the pnp is off-state, the collector current flows and a wrong signal is passed to the next step ciruits.

The influence of the dV/dt current on CMOS devices is significantly small as compared with that of bipolar devices because the active regions exist only in the surface in the MOS devices.

System Integration

Another prospective application of SOI technology is the automotive field, which requires large current DMOS outputs. Conventional pn junction-isolated power ICs are frequently used for these applications; however, the reliability of junction isolation is not sufficient. SOI DMOS power ICs will be used where high reliability is required.

For less than 100 V applications, the required thickness of buried oxide layer is less than 1 µm. The warpage of the SOI wafers is very small, and thus fine lithography can be applied. The same CMOS circuit library can be completely used without changes, because the same CMOS fabrication process can be applied without modification, if a relatively thick SOI layer is used.

This section shows the possibility of integration of an MPU together with BiCMOS analog circuits and 60 V power LDMOS. Four-bit MPUs, vertical npn, pnp, and 60 V power DMOS were fabricated on 2 µm SOI wafers by conventional 0.8 µm BiCMOS process [27]; 60 V DMOS can be fabricated using the CMOS p-well.

The fabricated 4-bit MPU, consisting of 30,000 FETs for core, 6000 FETs for cashe and 120,000 FETs for ROM, operated at a 20% faster clock speed of 50 MHz at 25°C as compared with 42 MHz of the bulk-version MPU, and even operated at above 200°C. It was found that clock speed could be improved and that a large latch-up immunity at high temperature was realized even if the MOSFETs were not isolated by trenches. The maximum operating temperature was more than 300°C. It was found that the yield of the MPU fabricated on SOI was the same as that on bulk wafers, verifying that the crystal quality of the currently available SOI wafers was sufficiently good. It was also found that both SOI and bulk MPUs could be operated at 300°C if MPUs consist of pure CMOS, although the power consumption of the bulk MPU was larger than that of the SOI MPUs.

One of the characteristic features of the SOI power IC structure, shown in Figure 7.43, is that there are no buried layers for bipolar transistors. It was found that vertical npn and pnp transistors fabricated on the n- and p-well layers exhibited sufficiently good characteristics, and the typical current gains hFE for the vertical npn and pnp transistors were 80 and 30, respectively.

All these results show that system integration including power LDMOS will be promising.