Power-Aware Architectural Synthesis:Architectural Synthesis Overview

Introduction

Power consumption is one of the most important parameters of modern electronic systems. It impacts the performance, cooling costs, packaging costs, and reliability of integrated circuits (ICs), as well as the life spans of battery-powered electronics. Therefore, it is important to consider power consumption during design.

The complexity and scope of automatic design continues to increase. It is now possible to automatically design, i.e., synthesize, complex ICs and systems from high-level specifications without designer intervention. Architectural synthesis has been an active research area for more than a decade. Since addressing power consumption at higher levels of the design process increases the potential for improvement, researchers have developed a wide range of power optimization and management techniques to address IC power consumption issues during architectural synthesis. In this chapter, we present techniques for the synthesis of low-power ICs and systems. In particular, we focus on power-aware behavioral synthesis and system synthesis.

The rest of this chapter is organized as follows. In Section 17.1.1, we introduce and define behavioral synthesis and system synthesis. In Section 17.2, we describe the contributors to IC and system power consumption and discuss a number of techniques to improve power and thermal characteristics. Many of these techniques will prove useful in both behavioral synthesis and system synthesis. In Sections 17.3 and 17.4, we provide details on behavioral synthesis and system synthesis and indicate areas of active research. Section 17.5 points out a few commercial architectural synthesis products. We conclude in Section 17.6.

Architectural Synthesis Overview

In 1958 and 1959, Jack Kilby and Robert Noyce independently built the first ICs. Although the simple applications of early ICs enabled fully manual design, within 10 years, engineers were designing large- scale integration (LSI) ICs containing tens of thousands of transistors. In the late 1960s and early 1970s, fully manual design became impractical and engineers began automating the design process. Table 17.1 gives a chronology of areas of active research and development in electronic design auto- mation. Note that the first research in an area may have appeared before the area was of wide interest, e.g., some researchers had already made great progress in behavioral synthesis before the 1990s. As indicated in Table 17.1, tasks that consist of simple actions repeatedly applied were the most straight- forward and the first to be automated. However, as design complexity continued to increase, engineers found it necessary to automate increasingly complicated and creative tasks that had once required the efforts of skilled designers. In recent years, two trends are apparent: higher levels of the design process have been automated and power consumption has become a first-order design characteristic. In the past 5 years, these trends have converged; research on power-aware architectural synthesis has pro- ceeded at a rapid pace.

Figure 17.1 illustrates the conventional levels or stages of digital system design. Physical design, i.e., deciding on the physical locations and shapes of transistors, functional units, and processors, as well as communication, clock distribution, and power distribution networks, was largely automated in the

1960s and 1970s. However, this area remains open, with continued improvement over past work and new algorithms to deal with changes brought about by process scaling. Combinational logic synthesis, the efficient design of combinational networks that implement Boolean expressions, advanced rapidly in the 1970s and 1980s. Register-transfer level (RTL) optimizations, such as retiming, underwent substantial advances in the 1990s.

This trend of automating increasingly high levels of the design process continues to this day. Sophisticated algorithms are now used to automatically design, or synthesize, very large-scale integration (VLSI) circuits and hardware–software systems, starting from high-level descriptions of application behavior. These synthesis algorithms automatically make design decisions at many levels, ranging from architectural level to physical level, to optimize performance, energy consumption, thermal characteristics, price, and reliability. Power consumption is now a critical cost for synthesized architectures. It influences packaging and cooling costs, performance, reliability, and battery life span. Moreover, optimizing power and thermal characteristics greatly increases the complexity of synthesis. This chapter provides a taxonomy of synthesis problems, describes how state-of-the-art synthesis algorithms solve these problems, and indicates trends that will influence future work in the field.

Architectural synthesis may be broken into two main areas: behavioral synthesis and system synthesis. This chapter describes these areas and explains methods of reducing power consumption during syn- thesis. However, each area is broad; they cannot be exhaustively covered here. System synthesis has its roots in hardware–software cosynthesis, with much current activity in system-on-chip (SoC) synthesis

and network-on-chip synthesis. This chapter describes hardware–software cosynthesis and SoC synthesis but defers to Marculescu’s Chapter 16 in this handbook for a detailed treatment of network-on-chip synthesis.

Behavioral synthesis and system synthesis share a few common challenges. In both cases, starting from an abstract description of the application to be implemented, constraints on the costs of the system (e.g., price, performance, and power consumption), and a database of resources that may be used to implement the application, it is necessary to determine which processing and communication resources will be used in the final design (allocation*), determine the resource that will be used for each particular operation and communication event (assignment), and provide a means of controlling the times at which all events occur (scheduling). These tasks are challenging; both the allocation/assignment and scheduling problems are NP-complete [1].† In summary, behavioral and system synthesis share a number of hard problems.

Behavioral synthesis differs from system synthesis as indicated in Figure 17.1 and Table 17.2. Behavioral synthesis and system synthesis can, in some cases, start from the same sorts of specifications. However, in behavioral synthesis, most operations are fine-grained, i.e., they can be represented by short instruction sequences for a general-purpose processor and may be implemented in hardware as a combinational network or a shallow pipeline, e.g., multiplication. In system-level synthesis, tasks are generally coarse-grained. They may be complex procedures requiring numerous general-purpose instructions or sequential hardware implementations, e.g., fast Fourier transform. In behavioral synthesis, it is generally assumed that the entire specification is implemented in synthesized hardware. In system synthesis, hardware and software are both used in the implementation. Differences in task granularity and implementation style (hardware-only or hardware–software) lead, in turn, to other differences between behavioral synthesis and system synthesis.

The simplicity of components, e.g., functional units and wires, in behavioral synthesis simplifies clocking, scheduling, and interface problems; it is usually possible to assume a globally synchronous system, a discrete time schedule in which all operations take small integer numbers of clock cycles, and straightforward interfacing between components. However, the simplicity of individual components is offset by their quantity. Quickly determining the impact of architectural decisions on the floorplans‡ and thermal profiles of designs containing hundreds or thousands of frequently parallel operations is extremely challenging.

In system synthesis, the number of components is limited. However, they are generally more compli- cated than arithmetic functional units, e.g., instruction processors or protocol translators. The system synthesis algorithm may not have control over the implementation of each complex component. There- fore, providing for global synchronization and communication is more challenging. Interface synthesis, i.e., synthesizing the interfaces between hardware components as well as software and hardware, is an †Garey and Johnson [1] provide an introduction to the theory of NP-completeness. For the purpose of this chapter, the implications can be summarized as follows: nobody has ever developed and reported an algorithm that can quickly produce optimal solutions to large instances of these problems and there is strong evidence (but no proof) that such an algorithm cannot be implemented using conventional, deterministic computers.

‡A floorplan indicates the positions of all architectural components in an IC.

active area of research in system synthesis. Unlike behavioral synthesis, tasks in system synthesis need not take a small integer number of clock cycles: time values are modeled as reals, not integers. Moreover, some operations may have dramatically higher execution times than others. Therefore, a number of discrete time domain scheduling algorithms that are promising in behavioral synthesis are not directly applicable in system synthesis.