Operational Trans conductance Amplifiers:Filter Applications with Low-Voltage Highly Linear OTAs.

By -
Filter Applications with Low-Voltage Highly Linear OTAs

Usually, Gm-C filters are considered suitable candidates for high-speed and low-power applications. Compared with the SC op-amp and RC op-amp techniques, the applicability of the Gm-C filter is limited by the low dynamic range and medium, even poor, linearity. A low-voltage, highly linear voltage- controlled transconductor [14, 15] shown in Figure 25.24 is used to implement a low-voltage, Gm-C all-pass adaptive forward equalizer (FE) stage operating at 125 Mbps. The adaptive forward equalizer is a part of a larger repeater/transceiver that enables IEEE 1394b transceivers to communicate over variable length of UTP-5 cables for up to 100 m. The repeater receives the data from one IEEE 1394b transceiver and retransmits it over the UTP-5 cable. On the other end of the cable, another repeater is used to receive the data (using the equalizer), and sends it to another IEEE 1394b transceiver. The equalizer is a cascade of two stages of the Gm-C stage shown in Figure 25.25. The control voltage is used to adapt the Gm of the transconductors, and consequently change the location of the poles in the forward equalizer. The control voltage is generated using an adaptive loop that estimates the attenuation introduced by the cable (which is a function of the cable length) and adjusts the response of the forward equalizer accordingly. To meet the jitter specification required for adequate performance of transceivers, the transconductor used in the forward equalizer stage has to have a THD of 30 dB or better at an input voltage range from 0 to 500 mV and data rate of 125 Mbps. Figure 25.26 shows the frequency response of the forward

Operational Transconductance Amplifiers-0331

Operational Transconductance Amplifiers-0332

equalizer as a function of control voltage. Note that the longer the cable is, the higher the control voltage becomes. The equalizer was implemented in a typical 180-nm digital CMOS process with a nominal supply voltage of 1.8 V, and adequate performance was achieved across process corners and temperature range of –40 to 125°C at supply voltage as low as 1.6 V. The transconductor occupied an area of 1945 µm2, and consumed an average power of 418 µW at 125 Mbps.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more