Microelectronics Packaging:Package Types and Through-Hole Packages

Package Types

IC packages have been developed over time to meet the requirements of high performance and small size. Figure 8.5 illustrates the size reduction of IC package over time. There are two types of packages for chip module to be connected to PC board: through-hole packages and surface-mount packages [3,7,32].

Through-Hole Packages

Through-hole mounting technology uses precision holes drilled through the board and plated with copper. This copper plating forms the connections between separate layers which consist of thin copper sheets stacked together and insulated by epoxy fiberglass. There are no dedicated via structures to make connections between wiring levels; through holes serve that purpose. The component leads are inserted into plated holes in the board and soldered. The advantage of through-hole package is that it forms a sturdy support for the chip carrier and resists thermal and mechanical stresses caused by the variations in the expansions of components at raised temperatures. Various types of through-hole packages are summarized in Table 8.7.

Surface-Mount Packages

In SMT, a chip carrier is soldered to the pads on the surface of a board without requiring any through holes. The advantages of SMT are smaller component sizes, lack of through holes, and the possibility of mounting chips on both sides of the PC board. This reduces package parasitic capacitances and induc- tances associated with the package pins and board wiring. SMT is the mainstream technology for second- level package. Various types of surface-mount packages are summarized in Table 8.8.

MultiChip Modules (MCMs)

In an MCM, several chips are supported on a single package. By eliminating one level of packaging, the inductance and capacitance of the electrical connections among the dice are reduced. There are several advantages of MCMs over single-chip carriers. The MCM minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuities between the chips mounted on the substrate by replacing the die-bump-interconnect-bump-die path. There are three primary categories of MCMs: MCM-C (cofire), MCM-D (deposit), and MCM-L (laminate). For MCM-C, modules are constructed on cofired ceramic or glass–ceramic substrates using thick-film screen printing technologies to form the conductor patterns (see Figure 8.4). The term “cofire” implies that the conductors and ceramic are fired at the same time. For MCM-D, modules are formed by the deposition of thin film metals on dielectrics, which may be polymers or inorganic dielectrics. Silicon substrates are used in some MCM-D (silicon-on-silicon pack- aging) to eliminate the mismatch of thermal expansion. For MCM-L, modules are constructed of plastic laminate-based dielectrics and copper conductors utilizing advanced forms of printed wiring board (PWB) technologies to form the copper interconnects and vias [8,33].

Chip Size Packages (CSPs)

The definition of CSP is that the package area (width) is less than 1.5 (1.2) times that of the chip area (width). CSPs can be divided into two categories: the fan-in type and the fan-out type.

A PGA has leads on its entire bottom surface. It has cavity-up and cavity-down versions. In a cavity- down version, a die is mounted on the same side as the pins facing toward the PC board, and a heat sink can be mounted on its backside to improve the heat flow. When the cavity and the pins are on the same side, the total number of pins is reduced because the area occupied by the cavity is not available for brazed pins. High pin count and larger power dissipation capability of PGAs make them attractive for different types of packaging Fan-in type CSPs are suitable for memory applications that have relatively low pin counts. Depending on the location of bonding pads on the chip surface, the fan-in type is further divided into two types: the center pad type and the peripheral pad type. The fan-in type CSP keeps all the solder bumps within the chip area by arranging bumps in area array format on the chip surface. The fan-out CSPs are used mainly for logic applications; because of the die size to pin count ratio, the solder bumps cannot be designed within the chip area [34,35].

Flip-Chip Package

Flip-chip technology employs soldering between the integrated circuit die face and the interconnect- ing substrate. The length of the electrical connections between the chip and the substrate can be

BGA packages transfer heat efficiently. The disadvantages of BGA packages are that solder connections cannot be visually inspected, and removed parts cannot be reused minimized by placing metallic bumps, usually solder, on the dice, flipping the chips over, aligning them with the contacts pads on the substrate, and reflowing the solder balls in a furnace to establish the bonding between the chips and the package [36,37]. Flip-chip bonding provides electrical con- nections with minute parasitic inductance and capacitance. Besides, contact pads are distributed over the entire chip surface. This saves silicon area, increases the maximum I/O and power/ground terminals available with a given die size, and provides more efficiently routed signal and power/ ground interconnections on the chip.

Three-Dimensional (3-D) packaging

The driving forces behind the development of 3-D packaging technology are similar to the multichip module technology, although the requirements for the 3-D technology are more aggressive. These requirements include the need for significant size and weight reductions, better system performance, higher packaging efficiency, smaller delay, higher reliability, higher number of input/output (I/O) contacts, and smaller operating power. Higher operating speed and lower power consumption can be realized because of the shorter signal paths between circuits that result from 3-D packaging. There are three categories of 3D packaging: (1) package-level 3-D packaging, in which packaged chips are stacked vertically; [38] (2) chip-level 3-D packaging, in which bare chips are stacked and then packaged [39–42]; and (3) wafer-level 3-D packaging, in which wafers are stacked and then diced and packaged (see Figure 8.6). Both package- and chip-level 3-D packagings are under production. Wafer-level 3-D packaging is a future technology and needs long development time. The key technologies for wafer-level

3-D packaging include: formations of via holes, buried interconnections, and micro-bumps; wafer thinning; wafer alignment and stacking; testing and evaluation of interconnection, micro-bumps and so on [43–46].