Bipolar Technology:Conventional Bipolar Technology

Conventional Bipolar Technology

Conventional bipolar technology is based on the device designs developed during the 1960s and 1970s. Despite its age, the basic concept still constitutes a workhorse in many commercial analog processes where ultimate speed and high packing density are not of primary importance. In addition, a conventional bipolar component is often implemented in low-cost BiCMOS processes.

Junction-Isolated Transistors

The early planar transistor technology took advantage of a reverse-biased pn junction in providing the necessary isolation between components. One of the earliest junction-isolated transistors, the so-called triple-diffused process, is simply based on three ion implantations and subsequent diffusion [55]. This device has been integrated into a standard CMOS process using one extra masking step [56]. The triple- diffused bipolar process, however, suffers from a large collector resistance owing to the absence of a subcollector, and the npn performance will be low.

By far, the most common junction-isolated transistor is represented by the device cross section of Figure 1.6, the so-called buried-collector process [55]. This device is based on the concept previously shown in Figure 1.2, but with the addition of an n+-collector plug and isolation. This is provided by the diffused p+ regions surrounding the transistor. The diffusion of the base and emitter impurities into the epilayer allows relatively good control of the base width (more details of the fabrication is given in the next section on oxide-isolated transistors).

The main disadvantage of the junction-isolated transistor is the relatively large chip area occupied by the isolation region, thus precluding the use of such a device in any VLSI application. Furthermore, high- speed operation is ruled out because of the large parasitic capacitances associated with the junction isolation and the relatively deep diffusions involved. Indeed, many of the conventional junction-isolated processes were designed for doping from the gas phase at high temperatures.

Oxide-Isolated Transistors

Oxide isolation permits a considerable reduction in the lateral and vertical dimensions of the buried- layer collector process. The reason is that the base and collector contacts can be extended to the edge of the isolation region. More chip area can be saved by having the emitter walled against the oxide edge. The principal difference between scaling of junction- and oxide-isolated transistors is visualized in Figure 1.7. The device layouts are Schottky clamped, i.e., the base contact extends over the collector region. This hinders the transistor from entering the saturation mode under device operation.

The process flow including mask layouts for an oxide-isolated bipolar transistor of the buried-layer collector type is shown in Figure 1.8 [57]. After formation of the subcollector by arsenic implantation through an oxide mask in the p– substrate, the upper collector layer is grown epitaxially on top (Figure 1.8[a]). The device isolation is fabricated by LOCOS or recessed oxide (ROX) process (Figures 1.8[b]–[d]). The isolation mask in Figure 1.8(b) is aligned to the buried layer using the step in the silicon (Figure 1.8[a]) originating from the enhanced oxidation rate for highly doped n+ silicon compared with the p– substrate during activation of the buried layer. The ROX is thermally grown (Figure 1.8[d]) after the boron field implantation

(or channel stop) (Figure 1.8[c]). This p+ implant is necessary for suppressing a conducting channel otherwise present under the ROX. The base is then formed by ion implantation of boron or BF2 through a screen oxide (Figure 1.8[d]); in the simple device of Figure 1.8, a single base implantation is used; in a more advanced bipolar process, the fabrication of the intrinsic and extrinsic base must be divided into one low dose and one high dose implantation, respectively, adding one more mask to the total flow. After base formation, an emitter/base contact mask is patterned in a thermally grown oxide (Figure 1.8[e]). The emitter is then implanted using a heavy dose arsenic implant (Figure 1.8[f]). An n+ contact is simultaneously formed in the collector window. After annealing, the device is ready for metallization and passivation.

Apart from the strong reduction in isolation capacitances, the replacement of a junction-isolated process with an oxide-isolated process also adds other high-speed features such as thinner epitaxial layer and shallower emitter/base diffusions. A typical base width is a few thousand angstroms and the resulting fT typically lies in the range of 1–10 GHz. The doping of the epitaxial layer is determined by the required breakdown voltage. Further speed enhancement of the oxide-isolated transistor is difficult due to the parasitic capacitances and resistances originating from contact areas and design-rule tolerances related to alignment accuracy.

Lateral pnp Transistors

The conventional npn flow permits the bipolar designer to simultaneously create a lateral pnp transistor, to be used, for example, as a bandgap reference. This is made by placing two base diffusions in close proximity to each other in the epilayer, one of them (pnp collector) surrounding the other (pnp emitter) (see Figure 1.9). In general, the lateral pnp device exhibits poor performance since the base width is determined by lithography constraints rather than vertical base control as in the npn device. In addition, there will be electron injection from the subcollector into the p-type emitter, thus reducing emitter efficiency.