Bipolar Technology:Advanced Bipolar Technology

Advanced Bipolar Technology

This section treats state-of-the-art production-ready bipolar technologies, with focus on optimized BiCMOS process for mixed-signal and RF applications. Examples are given of BiCMOS integration at the 0.25 µm CMOS technology node. Alongside the traditional down-scaling in design rules, efforts have

focused on new innovations in emitter and base-electrode fabrication. A key issue has been the integration of epitaxial SiGe intrinsic base into the standard npn process flow. For the emitter polysilicon electrode, in situ doping using both arsenic and phosphorus has been implemented for improved profile control and reduced influence of small emitter dimensions.

Bipolar integration on silicon-on-insulator (SOI) substrates is discussed with emphasis on thermal effects and self-heating. An example of process optimization resulting in reduced low frequency is given. This section concludes with an outlook on the future trends in bipolar technology after 2005.

Implanted Base

Today’s most advanced commercial processes are specified with an fT ~50 GHz [2, 7]. In these optimized processes, an in situ doped polysilicon emitter is used combined with rapid thermal processing for the final activation and drive-in of the emitter profile. In this way, an intrinsic base width of 500 nm with 12.3 kΩ pinch base resistance can be achieved. The major development has been carried out recently using double-poly technology, although similar performance has also been reported for quasi-self-aligned single-poly architectures [63, 68].

Since ion implantation is associated with a number of drawbacks such as channeling, shadowing effects, and crystal defects, it may be difficult to reach an fT >50–60 GHz based on such a technology. Also, the emitter implantation can be removed by utilizing in situ doped emitter technology (e.g., arsine [AsH3] gas during polysilicon deposition) [69]. Two detrimental effects are then avoided; namely, emitter perimeter depletion and the emitter plug effect [70]. The former effect causes a reduced doping concentration close to the emitter perimeter, whereas the latter implies the plugging of doping atoms in narrow emitter windows causing shallower junctions compared with larger openings on the same chip.

Arsenic came to replace phosphorus as the emitter impurity during the 1970s, mainly because of the emitter push-effect plaguing phosphorus monosilicon emitters. The phosphorus emitter has, however, experienced a renaissance in advanced bipolar transistors by introducing the so-called in situ phosphorus- doped polysilicon (IDP) emitter [71]. One motivation for using the IDP technology is the reduction in final emitter resistance compared with the traditional arsenic polyemitter, in particular for aggressively downscaled devices with very narrow emitter windows. In addition, the emitter drive-in for an IDP emitter is carried out at a lower thermal budget than the corresponding arsenic emitter owing to the difference in diffusivity between the impurity atoms.

Base electrode engineering in advanced devices has become an important field in reducing the total base resistance, thus improving the fmax of the transistor. One straightforward method in lowering the base sheet resistance is by shunting the base polysilicon with an extended silicide across the total base electrode. It is possible to realize fmax > 90 GHz in a production-ready double-poly process using TiSi2 [7].

Epitaxial Base

By introducing epitaxial film growth techniques for the intrinsic base formation, the base width is readily controlled up to the order of some hundred angstroms. In combination with the high current gain, which is obtained by the SiGe base-emitter heterojunction, this allows a very high base doping to be used. Hence, epitaxial base transistors feature comparable pinch-base resistance to implanted base transistors even though the base width is significantly reduced. Note that epitaxial base growth is not used for silicon- only transistors, owing to the added process complexity. In SiGe bipolar transistors, both selective and nonselective epitaxial growth (SEG and NSEG, respectively) are currently used. In a self-aligned double- poly approach, the SEG base epitaxy replaces the base implanation after emitter opening. This is schematically illustrated in Figure 1.15(a), shown directly after base epitaxy and prior to emitter poly deposition. This type of structure relies on a good thickness control and uniformity of the epitaxial growth to form the base link between the p+-poly overhangs and the SEG intrinsic base.

A self-aligned base-emitter structure can also be obtained for an NSEG base, which is formed in a blanket deposition, after completed device isolation. The purpose of the self-aligment is to minimize parasitics, such as the extrinsic base resistance, compared with the quasi-self-aligned structure, which has been widely used for this type (NSEG) of epitaxial base. In the 350 GHz transistor from IBM [72], the so-called raised extrinsic polysilicon base is formed self-aligned to a sacrificial emitter mandrel (see Figure 1.15[b]). The emitter-base dielectric isolation is also formed self-aligned to the mandrel.

must be used to reduce saturation owing to high resistance in the undepleted part of the lateral collector. This leads to a trade-off between a low breakdown voltage and high fT and fmax values.

Future Trends

The advances in silicon bipolar technology during the last 10-year period have been remarkable. While mixed-signal circuits for RF applications in the frequency range 1–10 GHz is still one of the main application areas, the outstanding performance of SiGeC epitaxial base bipolar transistors can be utilized for very demanding applications. State-of-the art technologies with cutoff frequencies above 300 GHz, gate delays below 4 ps are available and can be used to realize circuits operating at 100 GHz. Very high bit rates of 40–80 Gbit/s can be achieved and used for optical applications. In this area, SiGe technology will challenge high-performance III/V, (InP) bipolar technology. Integration of SiGe bipolars have been demonstrated in BiCMOS technologies at the 90 nm node and it is expected that the bipolar development will continue to follow the CMOS road map closely, where the BiCMOS solutions will be offered one or two technology nodes behind pure CMOS. The close connection to CMOS technology is seen, for example, in the choice of the metallization system. For contact metallization, nickel silicide is required in the sub-100 nm CMOS dimensions and has also been demonstrated in the SiGeC processes. An interesting application of nickel silicide technology is the demonstration of a metal emitter, developed to reduce the emitter resistance compared with the conventional polysilicon emitter technology, which has been used for more than 25 years. Bipolar technology also benefits directly from the recent transition to copper metallization, since this allows the devices to be scaled to higher current densities without concern for electromigration.

Among the most important goals for future bipolar technologies is to achieve high performance at low power dissipation. Operating at low current is also key to reduce the noise in very sensitive amplifiers. An important growing application area is automotive electronics, which has higher voltage requirements than the conventional ICs. The devices should also operate at elevated temperatures without performance degradation. A good uniformity and matching of device parameters is a traditional benefit of bipolar technology and will still make bipolar technology very competitive to deep submicron CMOS.