Bipolar Junction Transistor Circuits:Logic Circuits

Logic Circuits

The largest subclass of switching circuits is that of logic circuits [11]. Logic circuits are used to construct all systems that make numerical calculations such as computers and hand calculators. Logic systems are now designed in one of the two ways. The traditional method used since the late 1950s is to design the system using basic building blocks, such as AND gates, OR gates, NAND gates, NOR gates, inverters, flip-flops, and other timing circuits. These building blocks are interconnected to perform the overall functions required of the system. Several manufacturers provide IC chips to be used as the building blocks. Little or no circuit design is required to produce the finished system.

The second method is to realize the entire logic system as a system-on-a-chip (SOC). Computer firms design the entire central processing unit along with timing and memory units on a single silicon chip. All internal interconnections between building blocks are done on the chip with external pin connections provided only to interface with peripheral chips. In this case the design of the actual complex IC must be done to produce the logic system.

Building block logic circuits have been used since the 1950s in various forms. The early construction of logic gates was done on printed circuit boards using primarily discrete versions of BJTs, diodes, capacitors, and resistors. In the 1960s, ICs were utilized to create logic gates on a chip. Initially the IC contained two to four gates on a single chip. As the technology for making ICs improved, more gates could be fabricated on a single chip. The fabrication process has progressed through the small-scale integration (SSI) stage to the medium-scale integration (MSI) stage to the large-scale integration (LSI) stage to the very large-scale integration (VLSI) stage to the ultra large-scale integration (ULSI) stage.

Whereas the SSI chip may contain only a few gates requiring six transistors, the complex microcomputer chip might contain over 100 million transistors.

All levels of ICs are available at present. The building block approach uses SSI, MSI, and LSI chips in products that are produced in relatively small quantities. Gates and other logic circuits are generally mounted on printed circuit boards and interconnected to form the desired logic system. For more complex systems or systems that will sell high volumes, VLSI or ULSI technology is used to implement an SOC. When designing noncritical systems that are not pushing the limits of speed performance or power minimization, it is unnecessary for the logic designer to understand the details of the electronic circuits that make up the gates. The manufacturers have designed these and other logic circuits and specify key parameters that can be used in system design. These circuits are fabricated in several different configurations and from several types of device. Those chips having in common a particular device and configuration are said to belong to a logic family.

Some examples of currently useful families are transistor-transistor logic (TTL), emitter-coupled logic (ECL), and complementary MOS (CMOS) [11]. The TTL and ECL families are based on BJT circuits and are often applied to the building block approach. CMOS logic circuits are provided as building blocks and are also used for most computer SOC implementations. While the following discussion is oriented toward the building block approach, many of the considerations apply to the design of circuits on a single chip.

Within each family of logic are several categories or types of circuit. For example, the TTL family includes the conventional TTL, low-power, Schottky, low-power Schottky, advanced Schottky (AS), and advanced low-power Schottky (ALS) categories. All circuits of a given family must have compatible operating characteristics. The high-level voltage developed at the output of a gate must be sufficient to drive the input of any other gate to the same high level. The low-level output must pull the input of the next stage down to an acceptably low level. Certain current requirements must be met at each voltage level. Each category is compatible to some degree with other categories of the same family. For perfect compatibility, a single category is used for a given design. In general, an entire digital system will use only one or two logic-circuit families. Hundreds to thousands of SSI or MSI logic elements are connected properly to form the required subsystems of the digital system.

Sometimes it is necessary to connect logic elements that are not of the same family. When this is done, an interface between the different elements may be required. An interface consists of circuits that translate the output signals from one family to the input signals required by the other family. Certain families can be combined without interface circuits. A family is said to be compatible with another when both families can be interconnected without requiring interface circuits. Other combinations of families are popular enough that standard interface circuits are provided within the IC families.

Current and Voltage Definitions

To ensure proper operation when logic building blocks are interconnected, certain voltage and current requirements must be met. Some of the key parameters specified by manufacturers are the input/output current/voltages listed below.

(Current flowing out of a terminal has a negative value.)

When the output of Gate A is connected to the input of Gate B, the value of VOLmax for Gate A must be less than VILmax for Gate B and the value of VOHmin for Gate A must be greater than VIHmin for Gate B. In addition, the output currents of Gate A must be compatible with the input current requirements of Gate B for proper operation.

Fan-Out

In a digital system a given gate may drive the inputs to several other gates. The designer must be certain that the driving gate can meet the current requirements of the driven stages at both high and low voltage levels. The number of inputs that can be driven by the gate is referred to as the fan-out of the circuit. This figure is expressed in terms of the number of standard inputs that can be driven. Most circuits of a family will require the same input current, but a few may require more. If so, the specs for such a circuit will indicate that the input is equivalent to some multiple of standard loads. For example, a circuit may present an equivalent input of two standard loads. If fan-out of a gate is specified as 10, only five of these circuits could be safely driven. Figure 10.20 shows an AND gate loaded with four inputs, assuming each circuit presents one standard load to the AND gate output.

In several handbooks, the current requirements are given and fan-out can be calculated. For example, one TTL gate has the following current specs:

If this gate is to drive several other similar gates, we see that the output current capability of the stage is 10 times that required by the input. We note that the output stage can drive 400 mA into the following stages at the high level and sink 16 mA at the low level. The fan-out of this gate is 10.

Noise Margin

Although current requirement is the major factor in determining fan-out, input capacitance or noise margin may further influence this figure. Noise margin specifies the maximum amplitude noise pulse that will not change the state of the driven stage. This assumes that the driving stage presents a worst case logic level to the driven stage. Noise margin can be evaluated from a consideration of the voltage levels VIHmin, VILmax, VOHmin, and VOLmax. Figure 10.21 shows two logic circuits that are cascaded.

If we assume that VILmax = 0.8 V for circuit B, this means that the input must be <0.8 V to guarantee that circuit B interprets this value as a low level. If circuit A has a value of VOLmax = 0.4 V, a noise spike of less than the difference 0.8 - 0.4 V cannot lead to a level misinterpretation by circuit B.

 Since the minimum voltage developed by circuit A at the high level is 2.7 V, while circuit B requires only 2.0 V to interpret the signal as a high level, a negative noise spike of -0.7 V or less will not result in an error. As we consider the noise margin we recognize that the values calculated in Eq. (10.39) and Eq. (10.40) are worst case values. A particular circuit could have actual noise margins better than those calculated.

As more gate inputs are connected to a given output, the voltages generated at both high and low levels are affected as a result of increased current flow. Thus, fan-out is influenced by noise margin.

Switching Times

Another quantity which is used to characterize switching circuits is the speed with which the device responds to input changes. The preceding section discussed the factors that influence transistor switching times. For switching circuits, the graph of Figure 10.22 is useful in defining delay times [11]. This figure assumes an inverting gate.

There is a finite delay between the application of the input pulse and the output response. A quantitative measure of this delay is the difference in time between the point where Vin rises to 50% of its final value and the time when Vout falls to its 50% point. This quantity is called leading-edge delay tpHL. The trailing- edge delay tpLH is the time difference between 50% points of the trailing edges of the input and output signals. The propagation delay is defined as the average of tpHL and tpLH, or

Propagation delay time of an IC is a function of passive delay time, rise and fall times, and the saturation storage time of the circuit’s individual transistors. Since input and output capacitance will influence the IC switching times, fan-in and fan-out will also affect delay times. Switching times are sometimes specified by graphs showing the various times as functions of the number of standard input loads with specified driving conditions.

An understanding of the definitions given in the preceding paragraphs allows the designer to use logic gates as building blocks in digital systems. The TTL family has been the workhorse for many years in SSI and MSI applications. Fast and versatile, no other line offers as great a variety of circuits. The fabrication of resistors requires more chip volume than transistors do, and TTL chips use several resistors per gate. Consequently, applications in LSI circuits are somewhat limited.

ECL logic is the highest speed BJT family available. It does not offer as wide a variety of circuit types as TTL, but has been popular for use in high-speed applications such as supercomputers.

A TTL Logic Gate

The TTL family was originally based on the multiemitter construction of transistors shown in Figure 10.23 [11]. The operation of the input transistor can be visualized with the help of the circuit of Figure 10.24, which shows the bases of the three transistors connected in parallel, as are the collectors, whereas the emitters are separate

If all emitters are at ground level, the transistors will be saturated by the large base drive. The collector voltage will be only a few tenths of a volt above ground. The base voltage will equal VBE(on), which may be 0.5 V. If one or two of the emitter voltages are raised, the corresponding transistors will shut off. The transistor with an emitter voltage of 0 V will still be saturated, however; and saturation will force the base voltage and collector voltage to remain low. If all three emitters are raised to a higher level, the base and collector voltages will tend to follow this signal.

Returning to the basic gate of Figure 10.23, we see that when the low logic level appears at one or more of the inputs, Q1 will be saturated with a very small voltage appearing at the collector of this stage. Since at least 2VBE(on) must appear at the base of Q2 in order to turn Q2 and Q3 on, we can conclude that these transistors are off. When Q2 is off, the current through the 1.6-kW resistance is diverted into the base of Q4, which then drives the load as an emitter follower.

When all inputs are at the high voltage level, the collector of Q1 attempts to rise to this level. This turns Q2 and Q3 on, which clamps the collector of Q1 to a voltage of approximately 2VBE(on). The base–collector junction of Q1 appears as a forward-biased diode, whereas in this case the base–emitter junctions are reverse-biased diodes. As Q2 turns on, the base voltage of Q4 drops, decreasing the current through the load. The load current tends to decrease even faster than it would if only Q4 were present,

because Q3 is turning on to divert more current from the load. At the end of the transition, Q4 is off with Q2 and Q3 on. For positive logic, the circuit behaves as a NAND gate.

This arrangement of the output transistors is called a totem pole. In the emitter follower the output impedance is asymmetrical with respect to emitter current. As the emitter follower turns on, the output impedance decreases. Turning the stage off increases the output impedance and can lead to distortion of the load voltage especially for capacitive loads. The totem-pole output stage overcomes this problem.

Transistor Q3 is called the pull-down transistor and Q4 is called the pull-up transistor. The circuit is designed such that these two transistors are never on at the same time. If this occurred, Q3 may be destroyed because it cannot sink as much current as Q4 can provide. Only one of these stages will be on at any given time. If Q3 is on, the output voltage is pulled down toward ground; if Q4 is on, the output voltage is pulled up toward +5 V.

Although newer TTL gates are constructed differently from the basic gate, this configuration played a large role in digital design for three decades.

Emitter-Coupled Logic

ECL was developed in the mid-1960s and remains the fastest silicon logic circuit available. The two major disadvantages of ECL are (1) resistors, which require a great deal of IC chip area, must be used in each gate and (2) the power dissipation of an ECL gate is rather high. These two shortcomings limit the usage of ECL in VLSI systems. Instead, this family has been used for years in larger supercomputers that can afford space and power to achieve higher speeds.

The high speeds obtained with ECL are primarily based on two factors. No device in an ECL gate is ever driven into the saturation region and thus, saturation storage time is never involved as devices switch from one state to another. The second factor is that required voltage swings are not large. Voltage excursions necessary to change an input from the low logic level to the high logic level are minimal. Although noise margins are lower than other logic families, switching times are reduced in this way. Figure 10.25 shows an older ECL gate with two separate outputs. For positive logic, X is the OR output while Y is the NOR output.

Often the positive supply voltage is taken as 0 V and VEE as -5 V due to noise considerations. The diodes and emitter follower Q5 establish a temperature-compensated base reference for Q4. When inputs A, B, and C are less than the voltage VB, Q4 conducts while Q1, Q2, and Q3 are cut off. If any one of the inputs is switched to the first level, which exceeds VB, the transistor turns on and pulls the emitter of Q4 positive enough to cut this transistor off. Under this condition, output Y goes negative while X goes

positive. The relatively large resistor common to the emitters of Q1, Q2, Q3, and Q4 prevents these transistors from saturating. In fact, with nominal logic levels of -1.9 and -1.1 V, the current through the emitter resistance is approximately equal before and after switching takes place. Thus, only the current path changes as the circuit switches. This type of operation is sometimes called current mode switching. Although the output stages are emitter followers, they conduct reasonable currents for both logic level outputs and, therefore, minimize the asymmetrical output impedance problem.

In an actual ECL gate, the emitter follower load resistors are not fabricated on the chip. The newer version of the gate replaces the emitter resistance of the differential stage with a current source and replaces the bias voltage circuit with a regulated voltage circuit.

The ECL 100K family has gate propagation delay times around 0.75 ns compared with 2 ns for the older ECL 10K family [12]. The basic ECL architecture has also been extended to faster HBT devices similar to the original ECL logic families. Speed increases correspond to the improvement in gain- bandwidth figures of HBT devices over BJT devices. Propagation delay times of <100 ps are available in logic gates fabricated in InP.