Architecture and Design Flow Optimizations for Power-Aware FPGAs:FPGA Architectures.

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FPGA Architectures

We will start with the traditional view of an island-style FPGA (see Figure 20.1). It consists of a two- dimensional (2-D) array of configurable logic blocks (CLBs) in a sea of routing wires. These routing wires connect among themselves through programmable switches, forming switch blocks. Similarly, these wires also connect to the CLBs, forming connection boxes. We will use the term segment or wire to refer to a routing wire. A routing channel consists of multiple such wires. A net, in contrast, refers to a logical signal in the user design, which typically will be routed using a number of routing wires. The term channel width refers to the number of wires in the routing channel.

The modern FPGA has grown to be more complex than the one shown in Figure 20.1. Figure 20.2 shows the Virtex-2 FPGA architecture, which represents the state of the art. It stores the configuration

Architecture and Design Flow Optimizations for Power-Aware FPGAs-0086

information in SRAM cells, each of which consists of six transistors. The basic logic element in Virtex-2 is called a slice. A slice consists of two look up tables (LUTs), two flip-flops (FFs), fast carry logic, and some wide Muxes [11]. A CLB in turn consists of four slices and an interconnect switch matrix. The interconnect switch matrix consists of large multiplexers (as large as 32-to-1) controlled by configuration SRAM cells. Note that Figure 20.2 is not drawn to scale, and in reality the interconnect switches account for nearly 70% of the CLB area. The FPGA contains an array of such CLBs along with block RAMs (BRAMs), multipliers, and IO blocks. Altera’s FPGAs are also similar in technology to Virtex-2.

Antifuse-based FPGAs, offered by Actel, constitute a different category of FPGAs, which can be programmed only once. Actel and Lattice also manufacture some flash-based FPGAs. In this chapter, we will limit the discussion to SRAM-based FPGAs.

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