Technology Scaling and Low-Power Circuit Design:Technology Scaling Challenges

Introduction

Technologists and designers are encountering several challenges in maintaining historical rates of performance improvement and energy reduction with CMOS technology scaling as we entered the sub -100 nm technology generations, where we are introducing 65 nm technology to high-volume manufacturing. Researchers have identified barriers to continued scaling of technology and circuit power supply voltage [1]. For a microprocessor design to achieve high-performance and low-power, fundamental device physics issues such as transistor short-channel effects, device parameter variations, excessive subthreshold leakage, junction leakage, and gate oxide leakage show up at aggressively scaled technologies. Furthermore, some of the key bottlenecks are related to reducing device parasitics such as source/drain resistances and gate overlap capacitances. Excessive subthreshold and gate oxide leakage are emerging as serious problems. Functionality of special circuits such as wide fan-in domino circuits, SRAM cell stability, bitline delay scaling, and clock and interconnect power consumptions are issues that designers are facing. In addition, energy efficiency of the microarchitecture of general-purpose microprocessors is starting to play a more critical role in the performance versus power and area trade- offs. Potential solutions to the device technology scaling challenges at gate lengths approaching 10 nm are discussed in Section 21.2. Section 21.3 describes some promising circuit and design techniques to control leakage power. Energy-efficient microarchitecture trends are elucidated in Section 21.4.

Technology Scaling Challenges

Device Performance and Energy Scaling

Figure 21.1 plots technology nodes and transistor physical gate length in micrometers on the y-axis as a function of time on the x-axis. This plot shows that the actual transistor physical gate length dimension is more aggressive than the dimension of the technology node of interest. Nevertheless, we are continuing to scale the dimensions. In the sub-180 nm technology generations, it is difficult to maintain traditional constant electric-field supply voltage scaling (Figure 21.2 and Figure 21.3). Constant-field voltage scaling requires scaling of supply voltage as we scale the transistor gate length. If we scale the supply voltage, then we have to

scale the transistor threshold voltage similarly to sustain the required gate overdrive to maintain transistor drive current and performance. Figure 21.3 shows that we followed constant-field scaling from 0.6 µm technology node to 180 nm node. Owing to the nonscalability of threshold voltage from excessive leakage current considerations, threshold voltage has not been scaled aggressively and supply voltage has not scaled aggressively (aggressive means scaling by ~30% and less aggressive means scaling by ~15% which is less than the scaling factor of 30%). Consequently, we have not fulfilled true constant-field voltage scaling post 180 nm technology node. Essentially, the electric field across the gate dielectric has been increasing by 10% per generation because we have not reduced the supply voltage with the same scaling factor as we have scaled the gate oxide thickness. This has been made possible by the superior long-term reliability offered by physically thinner gate oxides. In order to improve the delay of driving constant capacitance loads such as those posed by interconnects in high-performance microprocessor designs, the transistor saturation current per unit width must remain constant or increase from one technology generation to the next. This performance gain has been accomplished by reducing the rate of supply voltage scaling (from 30% per generation to 15% per generation), clearly at the expense of increasing switching power density. Low-power circuit operation relies on aggressive scaling of supply voltage which has been challenged to maintain high-performance operation. Extrinsic source/drain resistance, gate overlap capacitance, and junction capacitance do not scale in a desired fashion. This limits the circuit delay improvements achievable from large intrinsic device saturation currents. Reducing the depth of the source/drain junction extension or tip (shallow junctions) improves short-channel effects and thus allows a shorter gate length. However, tip depth of <40 nm causes the tip resistance to become so large that the drive current becomes smaller. Figure 21.4 shows improvement in NMOS as well as PMOS transistor drive current as we reduce source/drain junction depths owing to improving the transistor’s electrostatics and its short-channel effects. However, transistor drive current has an optimum at approximately 40 nm. Below junction depths of 40 nm, one can observe that the transistor drive current becomes less owing to an increase in transistor source/drain resistance (what device engineers refer to as Rexternal). Increasing the tip doping concentration beyond the solid solubility limit can help alleviate this problem to some extent. However, this is very difficult to achieve. Furthermore, abruptness of the doping profiles, in vertical as well as lateral directions, must be increased to help out this limitation.

Spreading resistance from the inversion layer to the source/drain extension region also limits the drive current. This makes it difficult to scale the gate overlap length below 10 nm. Overlap is the region where source/drain junction extends under the gate. Overlap is required for transistor operation. However, its distance should be minimized to reduce parasitic gate overlap capacitance running across the width of the transistor at the source/drain to gate edge. Reducing this overlap distance below 10 nm impacts spreading resistance negatively and lowers transistor drive current and device performance.

Advanced bulk CMOS transistors use sophisticated channel implants including halo implant and retrograde well to assist designing a device that does not suffer from excessive short-channel effects (Figure 21.5). By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed. The objective is to optimize the channel doping profile to minimize transistor IOFF while maximizing transistor drive current, ION. Steep retrograde wells and halo implants have been extensively used in transistor scaling to achieve the above-mentioned objective [2–8]. The trend is in the direction of increasing channel doping, demanded by subsurface punch- through control and short-channel effect reduction. However, the increased doping causes capacitance of the gate-edge junction sidewall to increase with technology scaling. This degrades delays of wide-OR circuits such as bitlines in the cache. In spite of all these limitations, device and transistor delays represented by CV/I metric are reducing and delays well beyond a terahertz is achievable at sub-1 V supply voltages using a traditional planar bulk CMOS device structure in the 15–30 nm gate length regime (Figure 21.6 and Figure 21.7) [9–11].

A fully depleted SOI device structure, referred to as the depleted substrate transistor (DST) and ultrathin body MOSFETs are promising for alleviating many of the challenges discussed before

(Figure 21.8). The subthreshold swing is much steeper in the DST compared to either bulk or partially depleted SOI devices when the silicon film thickness is below 30 nm, resulting in a fully depleted channel. This allows Vt to be reduced for a specific leakage target and boosts the drive current. Furthermore, the oxide layer below the silicon channel completely eliminates subsurface punch-through and junction leakage currents. Therefore, channel doping can be reduced. This reduces the gate-edge junction sidewall capacitance dramatically.

The source/drain extension depth in the DST can be scaled by simply scaling the silicon thickness to improve short-channel effects. The buried oxide layer also serves as a diffusion stopper and creates more abrupt vertical doping profiles in the source/drain region. When combined with a raised source/drain structure, the drive current improvement owing to lower parasitic resistance is as much as 30%. The main challenge associated with further development of the DST with conventional polysilicon gates is achieving a sufficiently tight control of the silicon film thickness since the threshold voltage is quite sensitive to the film thickness. Control of this thickness is rather challenging, costly, and a key barrier before considering the DST as a viable transistor-architecture option in high-volume manufacturing.

This problem can be alleviated to some extent by migration to a metal gate electrode, whose work function is chosen appropriately to provide the appropriate Vt. Two different metals may be needed for NMOS and PMOS. When the gate length is pushed to the DIBL limit, threshold voltage sensitivity to variations in silicon film thickness will still need to be dealt with. In any case, the DST provides a promising scaling path to sub-20 nm technology generation.

Device researchers have been and are working very hard to provide paths for extending scaling of planar bulk CMOS transistors. Their key focus is on enhancing transport of carriers inside the channel of the transistor and trying to improve the off-state leakage characteristic of the transistor. Carrier mobility and transport enhancement help the transistor drive current and hence the speed. Off-state leakage can be helped if we improve the transistor subthreshold swing or how effectively the device transitions from the off state to the on state. The topic of leakage will be discussed more in the next section. Enhancing carrier channel transport properties has been achieved by strained Si [12–14] and more research is being conducted by new materials and structures that enable high mobility inside the transistor channel. Intel improved their transistor drive currents by optimization and enhancements of strain silicon techniques [12–14]. For PMOS, uniaxial strain was applied from raised source/drain regions by using epitaxial SiGe film. It was shown that channel strain was significantly improved by increasing Ge content in the SiGe film and optimizing the source–drain recess geometry. For NMOS, strain is applied through sacrificial films from the use of tensile cap films (Figure 21.9 and Figure 21.10). Research toward improving carrier mobility inside transistor channel has continued to such an extent that recently, compound semiconductors are being considered for channel of NMOS tran- sistors [15]. These researchers used indium antimonide (InSb) that has the highest electron mobility and saturation velocity among all known semiconductors to fabricate very fast switching field-effect transistors. Enhancing carrier mobility for NMOS is important as carrier mobility for PMOS can further get enhanced by strain. For future technologies, carbon nanotube transistors (CNTs) have shown that they have very high intrinsic carrier mobility [16,17]. But many technological limitations and research questions remain unanswered for these new material systems before they become a viable solution for advanced development.

Nonplanarmultigate structures and ultrathin body MOSFETs such as FinFETs [18] and trigate transistors [19] are an extension of fully depleted CMOS devices with better electrostatics and subthreshold slope that was discussed for DST and SOI technology earlier (Figure 21.11). DST can be viewed as single gate [20], FinFET is a double-gate structure, and trigate as its name applies has three gates that makes this device almost a surround gate structure with very good electrostatics. These structures provide better transistor scalability by enhancing device electrostatics. However, many integration challenges remain before these structures can be fabricated and make it into high-volume manufacturing. Furthermore, we need to make sure nonplanar devices provide more current in a given area footprint. Therefore, layout of these nonplanar devices should in effect provide the benefits of area scaling in accordance with Moore’s

21.2.2 Transistor Subthreshold and Gate Oxide Leakages

Subthreshold leakage current of a transistor is increasing by ~5X per generation (Figure 21.12 and Figure 21.13). At high temperature, it exceeds 1000 nA/µm in sub-100 nm technology nodes (Figure 21.14). As the physical gate oxide thickness approaches sub-10 Å regime, gate oxide leakage becomes <100 A/cm2 (Figure 21.15) owing to direct band-to-band tunneling. Although gate oxide

leakage increases weakly with temperature, it accelerates exponentially with increase in supply voltage at a rate of 2X larger leakage for every 100 mV increase in voltage. Junction leakage is an additional component of concern, since it is increasingly dictated by tunneling as channel doping concentrations approach 5 X 1018 cm−3 in the channel (Figure 21.16). These are the trends and unless we design the transistor architecture around these trends, they will be prohibitive.

There is a compelling need to use high-K dielectrics as the gate dielectric material to replace silicon dioxide or oxynitride. High-K dielectric materials would allow electrical thickness of the gate dielectric to be scaled to provide large capacitance per unit area, while keeping the tunneling leakage per unit area within acceptable limits owing to larger physical thickness. Scaling of electrical oxide thickness is essential to provide sharp subthreshold swing and large drive current and control short-channel effects. Charac- teristics of several candidate high-K dielectrics are compared in Figure 21.17. HfO2 and ZrO2 provide the smallest gate leakage, 2–3 orders of magnitude smaller than regular oxide, for a target electrical thickness in the sub-10 Å regime. Since the bandgap reduces with increasing permittivity, gate leakage owing to thermal emission dominates for materials with very high K values. Thus, Ta2O5 that has a very

high dielectric constant value is not as attractive for gate dielectric application. Of course, many process integration challenges need to be resolved and silicon-dielectric interface quality needs to be improved (for better reliability and higher carrier mobility) for these new dielectric materials to provide improve- ments to CMOS circuit delay.

The scaling of electrical gate oxide thickness is limited by poly depletion and separation of inversion layer charge from the oxide–silicon interface at high vertical fields owing to quantum-mechanical (QM) effects (Figure 21.18). Each of these effects adds approximately 5 Å to the effective electrical oxide thickness at the highest gate voltage. Even if we reduce the physical gate oxide thickness to almost zero in a polysilicon gate electrode system, we still see an effective electrical gate oxide thickness (owing to polydepletion and QM effects). These effects become more significant as the gate voltage increases. Thus, when averaged over the entire gate voltage range from Vt to the maximum supply voltage, their impacts on drive current are less severe. Nevertheless, to maximize the benefit of migrating to a high-K gate dielectric, polydepletion should be reduced or eliminated. Polydepletion has historically been reduced by doping the polysilicon gate electrode heavily. Increasing polydoping beyond the solid solubility limit is desirable. Transition to a metal gate fully eliminates polydepletion. But metal gates with appropriate work functions for NMOS and PMOS must be identified and process integration issues must be resolved. Combining metal gates with high-K dielectrics (in ultrathin fully depleted devices) to set the threshold voltage by work function engineering is a promising approach that also addresses the polydepletion problem. However, additional process complex- ities owing to two different gate electrode metals, one for NMOS and one for PMOS, will be incurred.

The trend in future transistor development will be toward using high-K dielectric with metal gates. Carrier mobility and transport will continue to improve and we may go toward nonplanar structures (ultrathin body, trigate, etc.) to enhance transistor electrostatics and short-channel effects. Advanced development of whatever solution scaling provides for us requires a tedious focus on reducing device parasitics. Transistors’ parasitic capacitances and series resistances are critical for efficient and cost- effective device integration before transistors are fabricated in high-volume manufacturing.