Technology Scaling and Low-Power Circuit Design:Delivering System Performance and Final Discussions

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Delivering System Performance and Final Discussions

Transistor performance improves every technology generation and part of it is due to increased transistor source/drain leakage (lowering Vt). This leakage has been increasing exponentially over several technology generations, and today it has become a substantial portion of the total power [27]. Circuits and microarchitectures have evolved to harvest transistor performance to deliver overall system performance, and this was a good strategy when the leakage was small. Now, and in the future, when source/drain leakage ceases to increase, limiting transistor performance, a new strategy must be adopted to deliver system performance. First, leakage avoidance, control, and tolerance should be comprehended in the architecture and circuits from day-one, and not as an after-thought. For example, activating stack effect when a logic block is in standby, or including sleep transistor control in the microarchitecture would allow you to increase transistor source/drain leakage and hence the performance. Second, architectures and circuits need to exploit transistor integration capacity, rather than raw transistor performance, to deliver overall performance. For example, Figure 21.39 shows a through- put-oriented architecture, where a logic block is replicated twice. Hypothetically, if you reduce supply voltage and frequency of the replicated design by 30%, you still get 40% more throughput, though with 30% reduction in each active and leakage power. The total transistors in the design doubled, but resulted in 40% more logic throughput, providing higher system performance. That is why microar- chitectures and circuits need to shift toward parallel throughput-oriented architectures, exploiting transistor integration capacity, to deliver higher system performance than simply depending on raw transistor performance. This will be extended to the concept of many-core in the future high-performance microprocessor design. The purpose of many core is to utilize parallelism in hardware not to achieve higher performance, but to lower power and improve system reliability. This approach may help in dealing with the challenge of higher variability.

Conclusions

We described CMOS scaling challenges for gate lengths approaching 10 nm and potential solutions in circuits and microarchitecture. These solutions may appear difficult, but are more mature and less risky than other proposed alternatives for CMOS. That is why, CMOS is, for now, and for the foreseeable future.

Technology Scaling and Low-Power Circuit Design-0120

Interactions among technologists, circuit designers, and architects have now become even more impor- tant to optimize the entire system particularly for low-power designs. Technology, circuits, and micro- architecture need to make concerted efforts to solve leakage, power and variation issues, and limitations.

Summary

Scaling of CMOS technology continues in spite of tremendous technology development barriers, design challenges, and prohibitive costs. Today, the 65 nm CMOS technology node is moving from development to high-volume manufacturing, while research and development continues on future technology nodes including 45 nm, 30 nm, and beyond.

However, the design of ICs in these scaled technologies faces growing limitations. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines spanning technology, fabrication, circuits, systems, design, and architecture.

On the technology front, the question arises whether we can continue to scale CMOS technology or whether we are close to the end of the ITRS road map. Should we continue along the traditional CMOS scaling path—reduce effective oxide thickness, improve channel mobility, and minimize parasitics—or consider a more radical departure from planar CMOS to nonplanar device structures such as tri-gate and FinFET thin body transistors? Can we translate the device electrostatic improvement to performance gain? On the design front, while researchers are exploring various circuit design techniques to deal with leakage and process variation, they have also started studying how to optimize circuits and systems with nonplanar CMOS devices.

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