System-Level Power Management And An Overview:Modeling Energy-Managed Computers

Modeling Energy-Managed Computers

An EMC models the electronic system as a set of interacting power manageable components (PMCs) controlled by one or more power managers (PMs). We model PMCs as black boxes. We are not concerned on how PMCs are designed; instead we focus on how they interact with each other and the operating environment. The purpose of this analysis is to understand what type and how much information should be exchanged between a power manager and system components to implement effective system-wide energy management policies. We consider PMCs in isolation first. Next, we describe DPM for systems with several interacting components.

Power Manageable Components

A PMC is defined to be an atomic block in an electronic system. PMCs can be as complex as a printed circuit board realizing an I/O device, or as simple as a functional unit within a chip. At the system level, a component is typically seen as a black box, i.e., no data is available about its internal architecture. The key attribute of a PMC is the availability of multiple modes of operation, which span the power–performance trade-off curve. Nonpower-manageable components are designed for a given performance target and power dissipation specification. In contrast, with PMCs, it is possible to dynamically switch between high-performance, high- power modes of operation and low-power, low-performance ones so as to provide just enough computational capability to meet a target timing constraint while minimizing the total energy consumption of completing a computational task. In the limit, one can think of a PMC to have a continuous range of operational modes. Clearly, as the number of available operational modes increases the ability to perform fine-grained control of the PMC to minimize the power waste and achieve a certain performance level increases. In practice, the number of modes of operation tends to be small because of the increased design complexity and hardware overhead of supporting multiple power modes.

Another important factor about a PMC is the overhead associated with the PMC transitioning from one mode of operation to next. Typically, this overhead is expressed as transition energy and a delay penalty. If the PMC is not operational during the transition, some performance is lost whenever a transition is initiated. The transition overhead depends on PMC implementation: in some cases the cost may be negligible, but, generally, it is not. Transition overhead plays a significant role in determining the number and type of operational modes enabled by the PMC designer. For example, excessive energy and delay overheads for transitions into and out of a given PMC state may make that state nearly useless because it will be very difficult to recompense the overheads unless the expected duration of contiguous time that the PMC remains in that state is especially long. Mathematically, one can represent a PMC by a finite-state machine where states denote the operational modes of the PMC and state transitions represent mode transition. Each edge in the state machine has an associated energy and delay cost. In general, low-power states have lower performance and larger transition overhead compared to high-power states. This abstract model is referred to as a power state machine (PSM).

Many single-chip components such as processors [1], memories [2], and archetypal I/O devices such as disk drives [3], wireless network interfaces [4], and displays [5] can readily be modeled by a PSM.

Example

The StrongARM SA-1100 processor [6] is an example of a PMC. It has three modes of operation: RUN, STDBY, and SLEEP. The RUN mode is the normal operating mode of the SA-1100: every on-chip resource is functional. The chip enters the RUN mode after successful power-up and reset. STDBY mode allows a software application to stop the CPU when it is not in use, while continuing to monitor interrupt requests on or off chip. In the STDBY mode, the CPU can be brought back to the RUN mode quickly when an interrupt occurs. SLEEP mode offers the greatest power savings and, consequently, the lowest level of available functionality. In the transition from RUN or STDBY, the SA-1100 performs an orderly shutdown of its on-chip activity. In a transition from SLEEP to any other state, the chip steps through a rather complex wake-up sequence before it can resume normal activity. The PSM model of the StrongARM SA-1100 is shown in Figure 15.1. States are marked with power dissipation and performance values, edges are marked with transition times and energy dissi- pation overheads. The power consumed during transitions is approximately equal to that in the RUN

mode. Notice that both STDBY and SLEEP have null performance, but the time for exiting SLEEP is much longer than that for exiting STDBY (10 µs versus 160 ms). In contrast, the wake-up time from the SLEEP state is much larger, and therefore, it must be carefully compared with the environment’s time constants before deciding to shut the processor down. In the limiting case of a workload with no idle periods longer than the time required to enter and exit the SLEEP state, a greedy policy which would shut down the processor as soon as an idle period was detected tends to reduce performance without actually saving any power (the ratio of the energy consumption divided by the transition time associated with any of the state transitions is of the same order of power dissipation in the RUN state). An external PM that controls the intermode transitions of the SA-1100 processor must observe the workload and make decisions according to a policy whose optimality depends on workload statistics and on predefined performance constraints. Notice that the policy becomes trivial if there are no performance constraints: the PM can keep the processor nearly always in the SLEEP state.