Silicon-on-Insulator Technology:Fabrication of SOI Wafers

Introduction

Silicon-on-insulator (SOI) technology, more specifically silicon-on-sapphire, was originally invented for the niche of radiation-hard circuits. In the last 25 years, a variety of SOI structures have been conceived with the aim of dielectrically separating, using a buried oxide (Fig. 3.1b), the active device volume from the silicon substrate [1,2]. Indeed, in an MOS transistor, only the very top region (0.1 to 0.2-mm thick, i.e., <0.1% of the total thickness) of the silicon wafer is useful for electron transport and device operation, whereas the substrate is responsible for detrimental, parasitic effects (Fig. 3.1a).

More recently, the advent of new SOI materials (Unibond, ITOX) and the explosive growth of portable microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power/ voltage and high-frequency CMOS circuits.

The aim of this chapter is to overview the state-of-the-art of SOI technologies, including the material synthesis (Section 3.2), the key advantages of SOI circuits (Section 3.3), the structure and performance of typical devices (Section 3.4), and the operation modes of fully depleted (FD; Section 3.5) and partially- depleted (PD) SOI MOSFETs (Section 3.6). Sections 3.7 and 3.8 are dedicated to small-geometry effects and innovative transistor architectures. The main challenges that SOI is facing, to successfully surpass bulk-Si in the commercial arena, are critically discussed in Section 3.9.

Fabrication of SOI Wafers

Many techniques, more or less mature and effective, are available for the synthesis of SOI wafers [1]. However, the overwhelming role is played by the Unibond and Smart-Cut processes.

Silicon on Sapphire

Silicon-on-sapphire (SOS, Fig. 3.2a1) is the initial member of the SOI family. The epitaxial growth of Si films on Al2O3 gives rise to small silicon islands that eventually coalesce. The interface transition region contains crystallographic defects owing to the lattice mismatch and Al contamination from the substrate. The electrical properties suffer from lateral stress, in-depth inhomogeneity of SOS films, and defective transition layer [3].

SOS has undergone a significant lifting: larger wafers (6 to 8 in) and thinner films (100 nm) with higher crystal quality and carrier mobility [4]. This improvement is achieved by solid-phase epitaxial regrowth. Silicon ions are implanted to amorphize the film and erase the memory of damaged lattice and interface. Annealing allows the epitaxial regrowth of the film, starting from the “seeding” surface toward the Si–Al2O3 interface.

Owing to the “infinite” thickness of the insulator, SOS is still attractive for the integration of RF and radiation-hard circuits.

ELO and ZMR

The epitaxial lateral overgrowth (ELO) method consists in growing a single-crystal Si film on a seeded and, often, patterned oxide (Fig. 3.2a2). Since the epitaxial growth proceeds in both lateral and vertical directions, the ELO process requires a post-epitaxy thinning of the Si film.

Alternatively, poly-silicon can be deposited directly on SiO2; subsequent zone melting recrystallization (ZMR) is achieved by scanning high-energy sources (lasers, lamps, beams, or strip heaters) across the wafer. The ZMR process can be seeded or unseeded; it is basically limited by the lateral extension of single-crystal regions, free from grain subboundaries and associated defects. ELO and ZMR are basic techniques for the integration of vertical and 3-D stacked circuits.

FIPOS

The full isolation by porous oxidized silicon (FIPOS) method makes use of the very large surface-to-volume ratio (103 cm2/cm-3) of porous silicon which is, thereafter, subject to selective oxidation (Fig. 3.2a3). The critical step is the conversion of selected p-type regions of the Si wafer into porous silicon, via anodic reaction. From a conceptual viewpoint, FIPOS can combine electroluminescent porous Si devices with fast SOI–CMOS circuits.

SIMOX

In the 1990s, the dominant SOI technology was separation by implantation of oxygen (SIMOX). The buried oxide (BOX) is synthesized by internal oxidation during the deep implantation of oxygen ions into a Si wafer. Annealing at high temperature (1320°C for 6 h) is necessary to recover a suitable crystalline quality

of the film. High current implanters (100 mA) have been conceived to produce 8 in wafers with good thickness uniformity, low defect density (except threading dislocations of 104 to 106 cm-2), sharp Si–SiO2 interface, robust BOX, and high carrier mobility [5].

The family of SOI structures is presented in Figure 3.2b.

• Thin and thick Si films fabricated by adjusting the implant energy.

• Low-dose SIMOX: a dose of 4 ´ 1017 O+ cm-2 and an additional oxygen-rich anneal for enhanced BOX integrity (ITOX process) yield a 0.1 mm thick BOX (Fig. 3.2b1).

• Standard SIMOX obtained with 1.8 ´ 1018 O+ cm-2 implant dose, at 190 keV and 650°C; the thicknesses of the Si film and BOX are roughly 0.2 and 0.4 mm, respectively (Fig. 3.2b2).

• Double SIMOX (Fig. 3.2b3), where the Si layer sandwiched between the two oxides can serve for interconnects, wave guiding, additional gates, or electric shielding.

• Laterally isolated single-transistor islands (Fig. 3.2b4), formed by implantation through a patterned oxide.

• Interrupted oxides (Fig. 3.2b5), which can be viewed as SOI regions integrated into a bulk Si wafer.

Wafer Bonding

Wafer bonding (WB) and etch-back stand as a more mature SOI technology. An oxidized wafer is mated to another SOI wafer (Fig. 3.2a4). The challenge is to drastically thin down one side of the bonded structure in order to reach the target thickness of the silicon film. Etch-stop layers can be achieved by doping steps (p+/p–, p/n), SiGe, or porous silicon. The advantage of WB is to provide unlimited combinations of BOX and film thicknesses, whereas its weakness comes from the dificulty to produce ultrathin films with good uniformity.

Unibond and Smart Cut

Unibond is a revolutionary bonding-related process which uses the deep implantation of hydrogen into an oxidized Si wafer (Fig. 3.2c1) to generate microcavities and thus circumvent the thinning problem [6,2]. After bonding wafer A to a second wafer B and subsequent annealing to enhance the bonding strength (Fig. 3.2c2), the hydrogen-induced microcavities coalesce. The two wafers separate, not at the bonded interface, but at a depth defined by the location of hydrogen microcavities. This mechanism, named Smart Cut, results in a rough SOI structure (Fig. 3.2c4). The process is completed by touch-polishing to erase the surface roughness.

The extraordinary potential of the Smart–Cut approach comes from several distinct advantages: (i) the etch-back step is avoided, (ii) the second wafer (Fig. 3.2c3) being recyclable, Unibond is a “single-wafer” process, (iii) only conventional equipment is needed for mass production of 8 to 12 in wafers, and (iv) the thickness of the silicon film and buried oxide can be adjusted to match most device configurations (ultra- thin CMOS or thick-film power transistors and sensors). The defect density in the film is very low, the electrical properties are excellent, and the BOX quality is comparable with that of the original thermal oxide. The Smart–Cut process is adaptable to a variety of materials: strained Si, Ge, SiGe, SiC or III–V compounds on insulator, silicon on diamond, etc. Smart Cut can be used to transfer already fabricated bulk-Si CMOS circuits on glass or on other substrates.

Eltran

Epitaxial layer transfer (Eltran) process is based on wafer bonding and splitting using porous silicon which is mechanically weak [7]. The thin Si film to be transferred is epitaxially grown on the porous layer and partially oxidized before the wafer is bonded to a handle wafer. Wafer splitting is achieved using a fine water jet. The residual porous silicon is etched away from the SOI wafer and the surface is smoothed by hydrogen annealing. Eltran features the same basic advantages as those listed for Smart Cut, the main difference being the splitting mechanism.

Silicon-On-Nothing (SON)

Silicon-on-nothing (SON) consists of selective epitaxy of sacrificial SiGe regions in a bulk-Si wafer. A silicon film (20 nm or thinner) is epitaxially grown on SiGe. The selective etching of the SiGe layer leaves an empty space (air gap) underneath the film, which can be filled with a dielectric to form a localized SOI structure, integrated in the bulk-Si wafer (as in Fig. 3.2b5) [8]. Alternatively, the suspended Si membrane can be used to fabricate gate-all-around transistors.