Silicon-on-Insulator Technology:Multiple-Gate SOI MOSFETs.

Multiple-Gate SOI MOSFETs

Innovative transistors with two or more gates are currently being explored for enhanced performance and functionality.

Double-Gate MOSFETs

Double-gate (DG) MOSFETs are ideal devices for electrostatic integrity and ultimate scaling below 10 nm channel length. The formation of front- and back-inversion channels enables volume inversion, which offers enhanced drain current and transconductance. The total inversion charge in DG-mode is roughly twice the inversion charge in single-gate (SG) mode and the subthreshold swing is ideal. The essential aspect is that the minority carriers flow in the middle of the film and experience less surface scattering, hence the mobility [41,46] and radiation hardness [47,10] are improved. Ernst et al. [39] reported an outstanding transcon- ductance increase by more than 200% for 3-nm-thick DG-mode transistor.

The two gates collaborate to provide an excellent electrostatic control, so that short-channel effects (DIBL, DIVSB, punch-through) are reduced. Numerical simulations including quantum effects, band- to-band tunneling, and direct source-to-drain tunneling recommend a body thickness-to-length ratio of roughly 1/2, a condition less stringent than in SG-MOSFETs (=1/4).

The main difficulty resides in devising a realistic and pragmatical technology. Several demonstrations are shown in Figure 3.10. Planar process is suitable in many respects, but cannot guarantee the self- alignment of the two gates. The DG technology can be greatly simplified if a reasonable degree of gate misalignment is tolerable. A possibility is to design a longer bottom gate, whereas the channel length is still defined by the source/drain implantation through the shorter top gate (Fig. 3.10c). Surprisingly, the transconductance and drive current may be higher than in “ideal” DG transistor with symmetrical self- aligned gates [48,49]. The reason is the dual action of the longer gate which contributes to volume inversion in the body and simultaneously to accumulation in the source/drain regions. This field-effect- junction mechanism contributes to the dynamic lowering of the series resistance. By optimizing the bottom gate length, the gain in transconductance compensates for the parasitic overlapping capacitance.

Such asymmetrical DG transistors have recently been fabricated starting from an SOI wafer and using a wafer-bonding technology. The bottom gate was made on top of the SOI film. This wafer is turned upside- down and bonded to a support Si wafer. After etching the substrate and BOX of the handling SOI wafer, the front gate was formed on the denuded side of the film, roughly aligned to the bottom gate (Fig. 3.10c). A totally different approach is the vertical DG MOSFET, where the source-body-drain stack and the current flow are perpendicular to the wafer surface. These devices are attractive because the channel length (i.e., body thickness) can be controlled by epitaxy, instead of e-beam lithography. They suffer however from the asymmetry of the source and drain terminals and from the difficulty of achieving tiny

pillars with ultrasmall inter-gate distances.

FinFETs are nonplanar DG transistors with relatively easy-to-implement process. In DG-FinFETs (Fig. 3.10f), the gate covers three sides of the body (fin) but the top channel is deactivated by using a thicker dielectric. The FinFET is a semi-vertical device because the current is controlled by the two vertical gates and flows horizontally along the body sidewalls.

A more advanced alternative (MIGFET) is to etch-off the top gate and provide independent contacts to the lateral gates. The advantage is that two gates can play different functions, so reducing the complexity of digital circuits [50].

Although the FinFET performance is promising, two critical scaling issues need to receive attention:

(i) the control of the crystal quality and orientation on the sidewalls by wet etching, and (ii) the trimming of the transistor body (inter-gate distance) to keep the short-channel effects under control [51,52].

Triple-Gate MOSFETs

A FinFET with an active top gate is called triple-gate MOSFET (TG-MOSFET). Actually, one single gate governs three different sections of the channel: two vertical and one horizontal (Fig. 3.10f). The gate dielectric should be equally thin on the three sides of the body to avoid multiple threshold voltages. The performance is encouraging. The magnitude of the current can be adjusted via the fin width, but this advantage is debatable because the scaling capability is inferior in wider fins.

By separating the contributions of the different channels, it was found that the carrier mobility is significantly degraded on the fin sidewalls as compared with the top and bottom channels [53]. Process refinements [51,52] and crystal orientation are under investigation to improve FinFET performance.

The coupling effects depend on the fin height, tsi, and width, W. A square TG-FinFET (tsi = W = 20 nm, Fig. 3.11a) features an inhomogeneous vertical variation of the electron concentration and surface potential on the lateral sides [54]. The “measured” threshold voltage corresponds to the lowest position-dependent VT . Corner effects may also become important, essentially in highly doped bodies.

A narrow and tall fin exhibits two distinct regions [54]. At the bottom of the device, the carrier distribution is inhomogeneous (2D, as in Fig. 3.11a), whereas in the upper region, the carrier profile becomes vertically homogeneous and quasi-1D in the lateral direction. The front channel and the upper regions of the lateral channels are in strong inversion. The electrostatics is controlled by the lateral gates, which can suppress the coupling to the bottom gate (Fig. 3.11b). This coupling coefficient saturates for an aspect ratio of tsi /W = 4 [54].

For thin and wide fins (tsi � W, as in FD MOSFETs), the lateral gates do not control the body well enough. Instead, the back-gate coupling is strong and modulates the front-channel conduction (Fig. 3.11b).

The geometry optimization aims to reach more current per fin (wider transistors) while avoiding too much sensitivity to substrate-effects. Even for a grounded back gate, a virtual substrate biasing can be induced by radiation, hot-carrier injection, or DIVSB effects. To achieve a low subthreshold swing, both dimensions W and tsi should be reasonably small (TG case) or one dimension must be very small.

If a very narrow body is manufacturable, the fringing fields are controlled by the lateral gates which define the back-surface potential, blocking the penetration of the fringing field from the drain (DIVSB). This control can be enhanced by allowing the lateral gates to extend vertically into the BOX (π-gate) and laterally underneath the film (Ω-gate) [10]. π-gate and Ω-gate architectures do relax the constraint of ultranarrow fins, but in turn require a thick enough BOX.

in wide, square, and tall fins (aspect ratios: tsi /W = 20/80, 20/20, and 80/20) (from Cristoloveanu et al., Int. J. High-Speed Electron., 2006, in press.)

At this point, it is worth underlining the 3D nature of the coupling effects:

• Lateral coupling between the side gates.

• Vertical coupling between the top gate and the bottom gate.

• Longitudinal coupling between the drain and the body via the fringing fields (DIVSB).

An ultimate and spectacular size effect is related to the transistor volume. FinFET technology is capable of releasing devices with all dimensions (thickness, width, and length) in the 10 nm range. A 10–18 cm3 body volume raises fundamental questions. For example, what doping level is induced by one single impurity? Does the impurity position matter? Should atomistic simulations include the silicon atoms one by one?

Gate-All-Around MOSFETs

The GAA technology (Fig. 3.10e), invented by Colinge et al. [10], is complex: (i) formation of a small- size Si membrane, (ii) thermal oxidation, and (iii) wrapping a homogeneous gate. The membrane can be processed in SOI by etching part of the BOX underneath the silicon film [10], or in bulk-Si by SON technology [8]: epitaxy of a sacrificial layer of SiGe, epitaxy of the thin Si film and, finally, removal of the SiGe layer (see Fig. 3.2b5). GAA MOSFETs can also have vertical pillar configuration. The formation of a pillar with small enough diameter is very challenging.

In GAA MOSFETs, the corner regions have a lower threshold voltage and turn on earlier than the main channel. This causes an increase of the leakage current in the off-state and poor subthreshold characteristics. Corner rounding equalizes the minority carrier distribution and suppresses the activation of the parasitic channels. A simpler solution for attenuating the corner effect is to leave the body undoped and adjust the threshold voltage with a midgap metal gate.

Four-Gate FET

The four-gate FET (G4-FET) is a genuine four-gate transistor operated in accumulation or depletion modes [55]. Figure 3.12a shows an inversion-mode, p-channel SOI MOSFET with two N+ body contacts. The same device becomes a G4-FET when the current is driven by electrons in the perpendicular direction. The majority carriers flow between the body contacts which play the role of source and drain for the G4-FET (Fig. 3.12a). There are four independent gates:

• The usual front and back MOS gates govern the surface accumulation or vertical depletion regions.

• The two lateral junctions control the effective width of the body through the extension of the horizontal depletion regions.

The conduction path is modulated by mixed MOS-JFET effects: from a wire-like volume conduction to strongly accumulated front- and back-interface channels. Different models explain the conduction mechanisms in surface accumulation or pure volume modes [56]. The G4-FET exhibits high current and transconductance and excellent subthreshold swing. Each gate has the capability of switching the tran- sistor on and off. The independent action of the four gates opens promising perspectives for novel applications: mixed-signal circuits, nanoelectronic devices (quantum wires), four-level logic functions with a reduced number of transistors, etc.

Note that the G4-FET accommodates naturally to scaling. As the gate length of CMOS circuits goes down, the width of the G4-FET is reduced increasing the junction–gate action. However, the G4-FET will not compete for minimum size, it will be more suitable for innovative circuit designs.

The most exciting aspect is the depletion-all-around (DAA) mode of operation. The majority carrier channel is surrounded by depletion regions. A quantum wire can be formed (Fig. 3.12b), the dimensions of which are vertically and laterally controlled by the gate bias, not by the lithography. The volume- conduction channel benefits from a double-shielding effect; it is separated from the interface, first by the depletion regions and second by the inversion layers. In the DAA mode, the device features maximum mobility, minimum noise, and unchallenged radiation hardness capability [57]. The G4-FET structure makes possible the independent cross-conduction of majority carriers (in the volume) and minority carriers (at the interfaces), which is a source for revolutionary devices.