Silicon-on-Insulator Technology:Generic Advantages of SOI

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Generic Advantages of SOI

SOI circuits consist of single-device islands dielectrically isolated from each other and from the underlying substrate (Fig. 3.1b). The lateral isolation offers more compact design and simplified technology than in bulk silicon: there is no need of wells or inter-device trenches. In addition, the vertical isolation achieves thin films, and eliminates most of the detrimental substrate effects (latch-up, punch-through, etc).

The source and drain regions extend down to the BOX, thus the junction surface is minimized. This implies reduced leakage currents and junction capacitances which further translates into improved speed, lower power dissipation, and wider temperature range of operation.

The limited extension of drain and source regions allows SOI devices to be less affected by short- channel effects, originated from ‘charge sharing’ between gate and junctions or from drain-induced barrier lowering. Besides the outstanding tolerance of transient radiation effects, SOI MOSFETs experi- ence a lower electric-field peak than in bulk Si and are potentially more immune to hot-carrier damage. It is in the highly competitive domain of low-voltage, low-power circuits, operated with one-battery supply (<1.5 V), that SOI can express its entire potential. A small gate voltage gap is suited to switch a transistor from off to on state. SOI offers the possibility to achieve a quasi-ideal subthreshold slope (60 mV/decade at room temperature), hence a threshold voltage below 0.3 V. Low leakage currents limit the static power dissipation, as compared with bulk Si, whereas the dynamic power dissipation is minimized by the combined effects of low parasitic capacitances and reduced voltage supply. Two arguments can be given to outline unequivocally the advantage of SOI over bulk Si:

• Operation at similar voltage consistently shows about 20 to 30% increase in speed, whereas operation at similar low-power dissipation yields as much as 300% performance gain in SOI. It is believed, at least in the SOI community, that SOI circuits of generation (n) and bulk-Si circuits from the next generation (n + 1) perform comparably.

• Bulk Si technology attempts to mimic a number of features that are natural in SOI: the double- gate configuration is reproduced by processing surrounded-gate vertical MOSFETs on bulk Si;. full depletion is approached by tailoring a low–high step doping, and the dynamic-threshold operation is borrowed from SOI.

The problem for SOI is that such an enthusiastic list of merits did not perturb the fantastic progress and authority of bulk Si technology. There was no room or need so far for an alternative technology such as SOI, which was utilized only for circuits with high added value. But, in the late 1990s, SOI has been included in the International Technology Roadmap of Semiconductors as the best suited CMOS option.

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