Silicon Carbide Technology:SiC Semiconductor Crystal Growth
SiC Semiconductor Crystal Growth
As of this writing, much of the outstanding theoretical promise of SiC electronics highlighted in the previous section has largely gone unrealized. A brief historical examination quickly shows that serious shortcomings in SiC semiconductor material manufacturability and quality have greatly hindered the development of SiC semiconductor electronics. From a simple-minded point of view, SiC electronics development has very much followed the general rule of thumb that a solid-state electronic device can only be as good as the semiconductor material from which it is made.
Historical Lack of SiC Wafers
Reproducible wafers of reasonable consistency, size, quality, and availability are a prerequisite for commercial mass production of semiconductor electronics. Many semiconductor materials can be melted and reproducibly recrystallized into large single crystals with the aid of a seed crystal, such as in the Czochralski method employed in the manufacture of almost all silicon wafers, enabling reasonably large wafers to be mass produced. However, because SiC sublimes instead of melting at reasonably attainable pressures, SiC cannot be grown by conventional melt-growth techniques. Prior to 1980, experimental SiC electronic devices were confined to small (typically ~1 cm2), irregularly shaped SiC crystal platelets grown as a byproduct of the Acheson process for manufacturing industrial abrasives (e.g., sandpaper) [32] or by the Lely process [33]. In the Lely process, SiC sublimed from polycrystalline SiC powder at temperatures near 2500°C are randomly condensed on the walls of a cavity forming small, hexagonally shaped platelets. While these small, nonreproducible crystals permitted some basic SiC electronics research, they were clearly not suitable for semiconductor mass production. As such, silicon became the dominant semiconductor fueling the solid-state technology revolution, while interest in SiC-based micro- electronics was limited.
Growth of 3C-SiC on Large-Area (Silicon) Substrates
Despite the absence of SiC substrates, the potential benefits of SiC hostile-environment electronics nevertheless drove modest research efforts aimed at obtaining SiC in a manufacturable wafer form. Toward this end, the heteroepitaxial growth of single-crystal SiC layers on top of large-area silicon substrates was first carried out in 1983 [34], and subsequently followed by a great many others over the years using a variety of growth techniques. Primarily owing to large differences in lattice constant (~20% difference between SiC and Si) and thermal expansion coefficient (~8% difference), heteroepitaxy of SiC using silicon as a substrate always results in growth of 3C-SiC with a very high density of crystallographic structural defects such as stacking faults, microtwins, and inversion domain boundaries [35]. Other large- area wafer materials besides silicon (such as sapphire, silicon-on-insulator, and TiC) have been employed as substrates for heteroepitaxial growth of SiC epilayers, but the resulting films have been of comparably poor quality with high crystallographic defect densities. The most promising 3C-SiC-on-silicon approach to date that has achieved the lowest crystallographic defect density involves the use of undulant silicon substrates [36]. However, even with this highly novel approach, dislocation densities remain very high compared to silicon and bulk hexagonal SiC wafers.
While some limited semiconductor electronic devices and circuits have been implemented in 3C-SiC grown on silicon, the performance of these electronics (as of this writing) can be summarized as severely limited by the high density of crystallographic defects to the degree that almost none of the operational benefits discussed in Section 5.3 has been viably realized. Among other problems, the crystal defects “leak” parasitic current across reverse-biased device junctions where current flow is not desired. Because excessive crystal defects lead to electrical device shortcomings, there are as yet no commercial electronics manufac- tured in 3C-SiC grown on large-area substrates. Thus, 3C-SiC grown on silicon presently has more potential as a mechanical material in microelectromechanical systems (MEMS) applications (Section 5.6.5) instead of being used purely as a semiconductor in traditional solid-state transistor electronics.
Growth of Hexagonal Polytype SiC Wafers
more crystal imperfections (see Section 5.4.5 below). This disparity is not surprising considering that silicon wafers have undergone nearly five decades of commercial process refinement.
SiC Epilayers
Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimation- grown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable and reproducible than bulk sublimation-grown SiC wafer material. Therefore, the controlled growth of high- quality epilayers is highly important in the realization of useful SiC electronics.
SiC Epitaxial Growth Processes
An interesting variety of SiC epitaxial growth methodologies, ranging from liquid-phase epitaxy, molec- ular beam epitaxy, and chemical vapor deposition(CVD) have been investigated [10,45]. The CVD growth technique is generally accepted as the most promising method for attaining epilayer reproducibility, quality, and throughputs required for mass production. In the simplest terms, variations of SiC CVD are carried out by heating SiC substrates in a chamber “reactor” with flowing silicon- and carbon-containing gases that decompose and deposit Si and C onto the wafer allowing an epilayer to grow in a well-ordered single-crystal fashion under well-controlled conditions. Conventional SiC CVD epitaxial growth pro- cesses are carried out at substrate growth temperatures between 1400°C and 1600°C at pressures from 0.1 to 1 atm resulting in growth rates of the order of a few micrometers per hour [10,41,46]. Higher temperature (up to 2000°C) SiC CVD growth processes, some using halide-based growth chemistries, are also being pioneered to obtain higher SiC epilayer growth rates of the order of hundreds of microme- ters per hour that appear sufficient for growth of bulk SiC boules in addition to very thick epitaxial layers needed for high-voltage devices [42,47,48].
Despite the fact that SiC growth temperatures significantly exceed epitaxial growth temperatures used for most other semiconductors, a variety of SiC CVD epitaxial growth reactor configurations have been developed and commercialized [41,46,49]. For example, some reactors employ horizontal reactant gas flow across the SiC wafer, while others rely on vertical flow of reactant gases; some reactors have wafers surrounded by heated “hot-wall” or “warm-wall” configurations, while other “cold-wall” reactors heat only a susceptor residing directly beneath the SiC wafer. Most reactors used for commercial production of SiC electronics rotate the sample to ensure high uniformity of epilayer parameters across the wafer. SiC CVD systems capable of simultaneously growing epilayers on multiple wafers have enabled higher wafer throughput for SiC electronic device manufacture.
SiC Epitaxial Growth Polytype Control
Homoepitaxial growth, whereby the polytype of the SiC epilayer matches the polytype of the SiC substrate, is accomplished by “step-controlled” epitaxy [50–52]. Step-controlled epitaxy is based upon growing epilayers on an SiC wafer polished at an angle (called the “tilt-angle” or “off-axis angle”) of typically 3°–8° off the (0 0 0 1) basal plane, resulting in a surface with atomic steps and relatively long, flat terraces between steps. When growth conditions are properly controlled and there is a sufficiently short distance between steps, Si and C adatoms impinging onto the growth surface find their way to step risers, where they bond and incorporate into the crystal. Thus, ordered, lateral “step-flow” growth takes place which enables the polytypic stacking sequence of the substrate to be exactly mirrored in the growing epilayer. SiC wafers cut with nonconventional surface orientations such as (1120) and (0338), provide a favorable surface geometry for epilayers to inherit stacking sequence (i.e., polytype) via step flow from the substrate [53,54].
When growth conditions are not properly controlled when steps are too far apart, as can occur with poorly prepared SiC substrate surfaces that are polished to within <1° of the (0 0 0 1) basal plane, growth adatoms island nucleate and bond in the middle of terraces instead of at the steps. Uncontrolled island nucleation (also referred to as terrace nucleation) on SiC surfaces leads to heteroepitaxial growth
of poor-quality 3C-SiC [51,52]. To help prevent spurious terrace nucleation of 3C-SiC during epitaxial growth, most commercial 4H- and 6H-SiC substrates are polished to tilt angles of 8° and 3.5° off the (0 0 0 1) basal plane, respectively. To date, all commercial SiC electronics rely on homoepitaxial layers that are grown on these “off-axis” prepared (0 0 0 1) c-axis SiC wafers.
Proper removal of residual surface contamination and defects left over from the SiC wafer cutting and polishing process is also vital to obtaining high-quality SiC epilayers with minimal dislocation defects. Techniques employed to better prepare the SiC wafer surface prior to epitaxial growth range from dry etching to chemical-mechanical polishing (CMP) [55]. As the SiC wafer is heated up in a growth chamber in preparation for initiation of epilayer growth, a high-temperature in-situ pregrowth gaseous etch (typically using H2 and/or HCl) is usually carried out to further eliminate surface contamination and defects [46,56,57]. It is worth noting that optimized pregrowth processing enables step-flow growth of high-quality homoepilayers even when the substrate tilt angle is reduced to <0.1° off-axis from the (0 0 0 1) basal plane [56]. In this case, axial screw dislocations are required to provide a continual spiral template of steps needed to grow epilayers in the <0 0 0 1> direction while maintaining the hexagonal polytype of the substrate [58].
SiC Epilayer Doping
In-situ doping during CVD epitaxial growth is primarily accomplished through the introduction of nitrogen (usually N2) for n-type and aluminum (usually trimethyl- or triethylaluminum) for p-type epilayers [10,59]. Some alternative dopants such as phosphorus and boron have also been investigated for the n-and p-type epilayers, respectively [59,60]. While some variation in epilayer doping can be carried out strictly by varying the flow of dopant gases, the site-competition doping methodology has enabled a much broader range of SiC doping to be accomplished [59,61]. In addition, site competition has also made moderate epilayer dopings more reliable and repeatable. The site-competition dopant- control technique is based on the fact that many dopants of SiC preferentially incorporate into either Si lattice sites or C lattice sites. As an example, nitrogen preferentially incorporates into lattice sites normally occupied by carbon atoms. By epitaxially growing SiC under carbon-rich conditions, most of the nitrogen present in the CVD system (whether it is a residual contaminant or intentionally introduced) can be excluded from incorporating into the growing SiC crystal. Conversely, by growing in a carbon-deficient environment, the incorporation of nitrogen can be enhanced to form very heavily doped epilayers for ohmic contacts. Aluminum, which is opposite to nitrogen, prefers the Si site of SiC, and other dopants have also been controlled through site competition by properly varying the Si/C ratio during crystal growth. SiC epilayer dopings ranging from 9 × 1014 to 1 × 1019 cm-3 are commercially available, and researchers have reported obtaining dopings over a factor of 10 larger and smaller than this range for the n- and p-type dopings [40]. The surface orientation of the wafer also affects the efficiency of doping incorporation during epilayer growth [54]. As of this writing, epilayers available for consumers to specify and purchase to meet their own device application needs have thickness and doping tolerances of ±25% and ±50%, respectively [40]. However, some SiC epilayers used for high-volume device production are far more optimized, exhibiting <5% variation in doping and thickness [41].
SiC Crystal Dislocation Defects
Table 5.2 summarizes the major known dislocation defects found in present-day commercial 4H- and 6H-SiC wafers and epilayers [10,39,41,62,63]. Since the active regions of devices reside in epilayers, the epilayer defect content is clearly of primary importance to SiC device performance. However, as evidenced by Table 5.2, most epilayer defects originate from dislocations found in the underlying SiC substrate prior to epilayer deposition. More details on the electrical impact of some of these defects on specific devices are discussed later in Section 5.6.
The micropipe defect is regarded as the most obvious and damaging “device-killer” defect to SiC electronic devices [64]. A micropipe is an axial screw dislocation with a hollow core (diameter of the order of a micrometer) in the SiC wafer and epilayer that extends roughly parallel to the crystallographic c-axis normal to the polished c-axis wafer surface [65–67]. These defects impart considerable local strain to the surrounding SiC crystal that can be observed using X-ray topography or optical cross polarizers [39,41,68,69]. Over the course of a decade, substantial efforts by SiC material vendors has succeeded in reducing SiC wafer micropipe densities nearly 100-fold, and some SiC boules completely free of micropipes have been demonstrated [10,41,70]. In addition, epitaxial growth techniques for closing SiC substrate micropipes (effectively dissociating the hollow-core axial dislocation into multiple closed-core dislocations) have been developed [71]. However, this approach has not yet met the demanding electronic reliability requirements for commercial SiC power devices that operate at high electric fields [72].
Even though micropipe “device-killer” defects have been almost eliminated, commercial 4H- and 6H- SiC wafers and epilayers still contain very high densities (>10,000 cm-2, summarized in Table 5.2) of other less-harmful dislocation defects. While these remaining dislocations are not presently specified in SiC material vendor specification sheets, they are nevertheless believed responsible for a variety of nonideal device behaviors that have hindered reproducibility and commercialization of some (particularly high electric field) SiC electronic devices [63,73,74]. Closed-core axial screw dislocation defects are similar in structure and strain properties to micropipes, except that their Burgers vectors are smaller so that the core is solid instead of a hollow void [66,67,75,76]. As shown in Table 5.2, basal plane dislocation defects and threading edge dislocation defects are also plentiful in commercial SiC wafers [39,62].
As discussed later in Section 5.6.4.1.2, 4H-SiC electrical device degradation caused by the expansion of stacking faults initiated from basal plane dislocation defects has hindered commercialization of bipolar power devices [63,74,77,78]. Similar stacking fault expansion has also been reported when doped 4H-SiC epilayers have been subjected to modest (~1150°C) thermal oxidation processing [79,80]. While epitaxial growth techniques to convert basal-plane dislocations into threading-edge dislocations have recently been reported, the electrical impact of threading-edge dislocations on the performance and reliability of high- electric field SiC devices remains to be fully ascertained [39]. It is also important to note that present- day commercial SiC epilayers still contain some undesirable surface morphological features such as “carrot defects” which could affect SiC device processing and performance [40,81,82].
In an exciting initial breakthrough, a Japanese team of researchers reported in 2004 that they achieved a 100-fold reduction in dislocation density in prototype 4H-SiC wafers of up to 3 in. in diameter [83]. While such greatly improved SiC wafer quality offered by this “multiple a-face” growth technique should prove highly beneficial to electronic (especially high-power) SiC device capabilities, it remains uncertain as of this writing as to when this significantly more complex (and therefore expensive) growth process will result in commercially viable mass-produced SiC wafers and devices.
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