Silicon Carbide Technology:SiC Device Fundamentals

SiC Device Fundamentals

To minimize the development and production costs of SiC electronics, it is important that SiC device fabrication takes advantage of existing silicon and GaAs wafer processing infrastructure as much as possible. As will be discussed in this section, most of the steps necessary to fabricate SiC electronics starting from SiC wafers can be accomplished using somewhat modified commercial silicon electronics processes and fabrication tools.

Choice of Polytype for Devices

As discussed in Section 4, 4H- and 6H-SiC are the far superior forms of semiconductor device quality SiC commercially available in mass-produced wafer form. Therefore, only 4H- and 6H-SiC device processing methods will be explicitly considered in the rest of this section. It should be noted, however, that most of the processing methods discussed in this section are applicable to other polytypes of SiC, except for the case of a 3C-SiC layer still residing on a silicon substrate, where all processing temperatures need to be kept well below the melting temperature of silicon (~1400°C). It is generally accepted that 4H-SiC’s substantially higher carrier mobility and shallower dopant ionization energies compared to 6H-SiC (Table 5.1) should make it the polytype of choice for most SiC electronic devices, provided that all other device processing,

performance, and cost-related issues play out as being roughly equal between the two polytypes. Further- more, the inherent mobility anisotropy that degrades conduction parallel to the crystallographic c-axis in 6H-SiC particularly favors 4H-SiC for vertical power device configurations (Section the 5.6.4). Because the ionization energy of the p-type acceptor dopants is significantly deeper than for the n-type donors, a much higher conductivity can be obtained for the n-type SiC substrates than for the p-type substrates.

SiC-Selective Doping: Ion Implantation

The fact that diffusion coefficients of most SiC dopants are negligibly small (at :::1800°C) is excellent for maintaining device junction stability, because dopants do not undesirably diffuse as the device is operated long term at high temperatures. Unfortunately, this characteristic also largely (except for B at extreme temperatures [84]) precludes the use of conventional dopant diffusion, a highly useful technique widely employed in silicon microelectronics manufacturing, for patterned doping of SiC.

Laterally patterned doping of SiC is carried out by ion implantation. This somewhat restricts the depth that most dopants can be conventionally implanted to <1 µm using conventional dopants and implan- tation equipment. Compared to silicon processes, SiC ion implantation requires a much higher thermal budget to achieve acceptable dopant implant electrical activation. Summaries of ion implantation pro- cesses for various dopants can be found in [85–96]. Most of these processes are based on carrying out implantation at temperatures ranging from room temperature to 800°C using a patterned (sometimes high-temperature) masking material. The elevated temperature during implantation promotes some lattice self-healing during the implant, so that damage and segregation of displaced silicon and carbon atoms does not become excessive, especially in high-dose implants often employed for ohmic contact formation. Co-implantation of carbon with dopants has been investigated as a means to improve the electrical conductivity of the more heavily doped implanted layers [88,95,97].

Following implantation, the patterning mask is stripped and a higher temperature (~1200 to 1800°C) anneal is carried out to achieve maximum electrical activation of dopant ions. The final annealing conditions are crucial to obtaining desired electrical properties from ion-implanted layers. At higher implant anneal temperature, the SiC surface morphology can seriously degrade [87,98]. Because subli- mation etching is driven primarily by loss of silicon from the crystal surface, annealing in silicon overpressures can be used to reduce surface degradation during high-temperature anneals [99]. Such overpressure can be achieved by close-proximity solid sources such as using an enclosed SiC crucible with SiC lid and/or SiC powder near the wafer, or by annealing in a silane-containing atmosphere. Similarly, robust deposited capping layers such as AlN and graphite, have also proven effective at better preserving SiC surface morphology during high-temperature ion implantation annealing [91,92].

As evidenced by a number of works, the electrical properties and defect structure of 4H-SiC doped by ion implantation and annealing are generally inferior to SiC doped in-situ during epitaxial growth [89,100–103]. Naturally, the damage imposed on the SiC lattice roughly scales with implantation dose. Even though reasonable electrical dopant activations have been achieved, thermal annealing pro- cesses developed to date for SiC have not been able to thoroughly repair all damage imposed on the crystal lattice by higher-dose ion implantations (such as those often used to form heavily doped layers in preparation of ohmic contact formation, Section 5.5.3). The degraded crystal quality of highly implanted SiC layers has been observed to degrade carrier mobilities and minority carrier lifetimes, thereby causing significant degradation to the electrical performance of some devices [90,103]. Until large further improvements to ion-implanted doping of SiC are developed, SiC device designs will have to account for nonideal behavior associated with SiC-implanted layers.

SiC Contacts and Interconnect

All useful semiconductor electronics require conductive signal paths in and out of each device as well as conductive interconnects to carry signals between devices on the same chip and to external circuit elements that reside off-chip. While SiC itself is theoretically capable of fantastic electrical operation

under extreme conditions (Section 5.3), such functionality is useless without contacts and interconnects that are also capable of operation under the same conditions. The durability and reliability of metal–semiconductor contacts and interconnects are one of the main factors limiting the operational high-temperature limits of SiC electronics. Similarly, SiC high-power device contacts and metallizations will have to withstand both high temperature and high current density stress never before encountered in silicon power electronics experience.

The subject of metal–semiconductor contact formation is a very important technical field too broad to be discussed in great detail here. For general background discussions on metal–semiconductor contact physics and formation, the reader should consult narratives presented in References 15 and 104. These references primarily discuss ohmic contacts to conventional narrow-bandgap semiconductors such as silicon and GaAs. Specific overviews of SiC metal–semiconductor contact technology can be found in References 105–110.

As discussed in References 105–110, there are both similarities and a few differences between SiC contacts and contacts to conventional narrow-bandgap semiconductors (e.g., silicon, GaAs). The same basic physics and current transport mechanisms that are present in narrow-bandgap contacts such as surface states, Fermi-pinning, thermionic emission, and tunneling, also apply to SiC contacts. A natural consequence of the wider bandgap of SiC is the higher effective Schottky barrier heights. Analogous with narrow-bandgap ohmic contact physics, the microstructural and chemical state of the SiC–metal interface is crucial to contact electrical properties. Therefore, premetal-deposition surface preparation, metal deposition process, choice of metal, and post-deposition annealing can all greatly impact the resulting performance of metal–SiC contacts. Because the chemical nature of the starting SiC surface is strongly dependent on surface polarity, it is not uncommon to obtain significantly different results when the same contact process is applied to the silicon face surface versus the carbon face surface.

SiC Ohmic Contacts

Ohmic contacts serve the purpose of carrying electrical current into and out of the semiconductor, ideally with no parasitic resistance. The properties of various ohmic contacts to SiC reported to date are summarized elsewhere [107–110]. While SiC-specific ohmic contact resistances at room temperature are generally higher than in contacts to narrow-bandgap semiconductors, they are nevertheless sufficiently low for most envisioned SiC applications. Lower specific contact resistances are usually obtained to n- type than to p-type 4H- and 6H-SiC. Consistent with narrow-bandgap ohmic contact technology, it is easier to make low-resistance ohmic contacts to heavily doped SiC and thermal annealing is almost always employed to promote favorable interfacial reactions.

Truly enabling harsh-environment SiC electronics will require ohmic contacts that can reliably with- stand prolonged harsh-environment operation. Most reported SiC ohmic metallizations appear sufficient for long-term device operation up to 300°C. SiC ohmic contacts that withstand heat soaking under no electrical bias at 500–600°C for hundreds or thousands of hours in nonoxidizing gas or vacuum envi- ronments have also been demonstrated [110]. Only recently has successful long-term electrical operation of n-type ohmic contacts in oxidizing 500–600°C air ambients been demonstrated in relatively low- current density devices [111,112]. Further research is needed to obtain similarly durable high-temperature contacts to p-type SiC. Electromigration, oxidation, and other electrochemical reactions driven by high- temperature electrical bias in a reactive oxidizing environment are likely to limit SiC ohmic contact reliability for the most demanding applications that simultaneously require both high temperature and high power (i.e., high current density). The durability and reliability of SiC ohmic contacts is one of the critical factors limiting the practical high-temperature limits of SiC electronics.

SiC Schottky Contacts

Rectifying metal–semiconductor Schottky barrier contacts to SiC are useful for a number of devices, including commercialized SiC metal–semiconductor field-effect transistors (MESFETs) and fast-switching rectifiers [40,113]. References 105, 106, 108, and 114 summarize electrical results obtained in a variety of SiC Schottky studies. Owing to the wide bandgap of SiC, almost all unannealed metal contacts to lightly doped 4H- and 6H-SiC are rectifying. Rectifying contacts permit extraction of Schottky barrier heights and diode ideality factors by well-known current–voltage (I–V) and capacitance–voltage (C–V) electrical measurement techniques [104]. While these measurements show a general trend that Schottky junction barrier height does somewhat depend on metal–semiconductor work function difference, the dependence is weak enough to suggest that surface state charge also plays a significant role in determining the effective barrier height of SiC Schottky junctions. At least some experimental scatter exhibited for identical metals can be attributed to surface cleaning and metal deposition process differences, as well as different barrier height measurement procedures. For example, the work by Teraji et al. [115], in which two different surface-cleaning procedures prior to titanium deposition lead to ohmic behavior in one case and rectifying behavior in the other, clearly shows that the process plays a significant role in determining SiC Schottky contact electrical properties.

It is important to note that nonuniformities in electrical behavior, many of which have been traced to SiC crystal defects (Section 5.4.5) have been documented to exist across the lateral area of most SiC Schottky contacts with areas >10-4 cm2 [116–118]. Furthermore, the reverse current drawn in experi- mental SiC diodes, while small, is nevertheless larger than expected based on theoretical substitution of SiC parameters into well-known Schottky diode reverse leakage current equations developed for narrow- bandgap semiconductors. Models based on spatially localized Schottky barrier lowering as well as quan- tum mechanical tunneling owing to higher SiC electric fields, have been proposed to explain the nonideal reverse leakage behavior of SiC Schottky diodes [119–121]. In addition, electric field crowding along the edge of a SiC Schottky contact can also lead to increased reverse-bias leakage current and reduced reverse breakdown voltage [15,18,104]. Edge-termination techniques to relieve electric field edge crowding and improve Schottky rectifier reverse properties are briefly discussed later in Section 5.6.4. The practical operation of rectifying SiC Schottky diodes is usually limited to temperatures below 400°C; above this temperature, reverse-bias thermionic emission leakage current and thermally driven SiC–metal interface degradation (via material intermixing and chemical reactions) tend to become undesirably large.

Patterned Etching of SiC for Device Fabrication

At room temperature, there are no known conventional wet chemicals that etch single-crystal SiC. Most patterned etching of SiC for electronic devices and circuits is accomplished using dry etching techniques. The reader should consult References 122–124 which contain summaries of dry SiC etching results obtained to date. The most commonly employed process involves reactive ion etching (RIE) of SiC in fluorinated plasmas. Sacrificial etch masks (such as aluminum metal) are deposited and photolithograph- ically patterned to protect desired areas from being etched. The SiC RIE process can be implemented using standard silicon RIE hardware and typical 4H- and 6H-SiC RIE etch rates of the order of hundreds of angstroms per minute. Well-optimized SiC RIE processes are typically highly anisotropic with little undercutting of the etch mask, leaving smooth surfaces. One of the keys to achieving smooth surfaces is preventing “micromasking”, wherein the masking material is slightly etched and randomly redeposited onto the sample effectively masking very small areas on the sample that were intended for uniform etching. This can result in “grass”-like etch-residue features being formed in the unmasked regions, which is undesirable in most cases.

While RIE etch rates are sufficient for many electronic applications, much higher SiC etch rates are necessary to carve features of the order of tens to hundreds of micrometers deep that are needed to realize advanced sensors, MEMS, and through-wafer holes useful for SiC RF devices. High-density plasma dry- etching techniques such as electron cyclotron resonance and inductively coupled plasma have been developed to meet the need for deep etching of SiC. Residue-free patterned etch rates exceeding a thousand angstroms a minute have been demonstrated [122,123,125–128].

Patterned etching of SiC at very high etch rates has also been demonstrated using photo-assisted and dark electrochemical wet etching [129,130]. By choosing proper etching conditions, this technique has demonstrated a very useful dopant-selective etch-stop capability. However, there are major incompatibilities of the electrochemical process that make it undesirable for VLSI mass production, including extensive preetching and postetching sample preparation, etch isotropy and mask undercutting, and somewhat nonuniform etching across the sample. Laser etching techniques are capable of etching large features, such as via through-wafer holes useful for RF chips [131].

SiC Insulators: Thermal Oxides and MOS Technology

The vast majority of semiconductor-integrated circuit chips in use today rely on silicon metal-oxide– semiconductor field-effect transistors (MOSFETs), whose electronic advantages and operational device physics are summarized in Katsumata’s chapter and elsewhere [15,18,132]. Given the extreme usefulness and success of inversion channel MOSFET-based electronics in VLSI silicon (as well as discrete silicon power devices), it is naturally desirable to implement high-performance inversion channel MOSFETs in SiC. Like silicon, SiC forms a thermal SiO2 when it is sufficiently heated in an oxygen environment. While this enables SiC MOS technology to somewhat follow the highly successful path of silicon MOS technology, there are nevertheless important differences in insulator quality and device processing that are presently preventing SiC MOSFETs from realizing their full beneficial potential. While the following discourse attempts to quickly highlight key issues facing SiC MOSFET development, more detailed insights can be found in References 133–142.

From a purely electrical point of view, there are two prime operational deficiencies of SiC oxides and MOSFETs compared to silicon MOSFETs. First, effective inversion channel mobilities in most SiC MOS- FETs are lower than one would expect based on silicon inversion channel MOSFET carrier mobilities. This seriously reduces the transistor gain and current-carrying capability of SiC MOSFETs, so that SiC MOSFETs are not nearly as advantageous as theoretically predicted. Second, SiC oxides have not proven as reliable and immutable as well-developed silicon oxides, in that SiC MOSFETs are more prone to threshold voltage shifts, gate leakage, and oxide failures than comparably biased silicon MOSFETs. In particular, SiC MOSFET oxide electrical performance deficiencies are attributed to differences between silicon and SiC thermal oxide quality and interface structure that cause the SiC oxide to exhibit undesirably higher levels of interface state densities (~1011–1013 eV-1 cm-2), fixed oxide charges (~1011–1012 cm-2), charge trapping, carrier oxide tunneling, and lowered mobility of inversion channel carriers.

In highlighting the difficulties facing SiC MOSFET development, it is important to keep in mind that early silicon MOSFETs also faced developmental challenges that took many years of dedicated research efforts to successfully overcome. Indeed, tremendous improvements in 4H-SiC MOS device performance have been achieved in recent years, giving hope that beneficial 4H-SiC power MOSFET devices for operation up to 125°C ambient temperatures might become commercialized within the next few years. For example, 4H-SiC MOSFET inversion channel mobility for conventionally oriented (8° off (0 0 0 1) c-axis) wafers has improved from <10 to >200 cm2/V-1s-1, while the density of electrically detrimental SiC–SiO2 interface state defects energetically residing close to the conduction band edge has dropped by an order of magnitude [141,143,144]. Likewise, alternative SiC wafer surface orientations such as (1120) and (0338) that are obtained by making devices on wafers cut with different crystallographic orientations (Section 5.2.1), have also yielded significantly improved 4H-SiC MOS channel properties [54,139]. One key step to obtaining greatly improved 4H-SiC MOS devices has been the proper introduction of nitrogen-compound gases (in the form of N2, NO, N2O, or NH3) during the oxidation and post- oxidation annealing process [136,137,141,142]. These nitrogen-based anneals have also improved the stability of 4H-SiC oxides to high electric field and high-temperature stressing used to qualify and quantify the reliability of MOSFETs [140]. However, as Agarwal et al. [145] have pointed out, the wide bandgap of SiC reduces the potential barrier impeding tunneling of damaging carriers through oxides grown on 4H-SiC, so that 4H-SiC oxides cannot be expected to attain identical high reliability as thermal oxides on silicon. It is highly probable that alternative gate insulators besides thermally grown SiO2 will have to be developed for optimized implementation of inversion channel 4H-SiC insulated gate transistors for the most demanding high-temperature and high-power electronic applications. As with silicon MOSFET technology, multilayer dielectric stacks will likely be developed to further enhance SiC MOSFET performance [133,146].

SiC Device Packaging and System Considerations

Hostile-environment SiC semiconductor devices and ICs are of little advantage if they cannot be reliably packaged and connected to form a complete system capable of hostile-environment operation. With proper material selection, modifications of existing IC packaging technologies appear feasible for non- power SiC circuit packaging up to 300°C [147]. Recent work is beginning to address the needs of the most demanding aerospace electronic applications, whose requirements include operation in high- vibration 500–600°C oxidizing-ambient environments, sometimes with very high power [7,148–152]. For example, some prototype electronic packages and circuit boards that can withstand over a thousand hours at 500°C have been demonstrated. Harsh-environment passive components such as inductors, capacitors, and transformers, must also be developed for operation in demanding conditions before the full system-level benefits of SiC electronics discussed in Section 5.3 can be successfully realized.