Power IC Technologies:Power Output Devices

Power Output Devices

Output devices are most important part of power ICs. A whole power system can be integrated on a single silicon chip if high-voltage power devices can be integrated with analog and digital circuits as well as MPUs. Recently, MOS gate power devices are primarily adopted because of the low on-resistance and the ease of gate control. These are DMOSFETs and IGBTs.

Lateral Power MOSFET

pn junction-isolated power ICs are frequently used for low-voltage applications, where DMOS is primary choice for output devices. Since the reliability of junction isolation is not sufficient, SOI DMOS power ICs will be used where high reliability is required. In this section, DMOS electrical characteristics are described, using mostly the junction-isolated DMOS data.

For above 60 V breakdown voltage range, the vertical DMOS structure with upside surface drain contact (up-drain DMOS, see Figure 7.25) has conventionally been used. However, recently, the lateral DMOS (LDMOS) structure (Figure 7.26) tends to be used for the entire voltage range. This is because LDMOS on-resistance can be directly improved by adopting finer lithography. In contrast, up-drain vertical DMOS on-resistance includes the resistances of the buried n+ layer and the sinker plug diffusions, which are not improved by finer lithography.

Figure 7.27 shows the state-of-the-art DMOS on-resistance as a function of breakdown voltage. The figure also shows the state-of-the-art on-resistance for vertical discrete trench MOSFETs as a comparison. Black squares show lateral DMOS, and triangles show trench MOSFETs. Recently, battery-operated mobile equipment and computer peripherals have opened large application fields, and lateral MOSFETs of less than 60 V are the major output devices. It is an interesting fact that the state-of-the-art on- resistances of lateral DMOS and vertical trench MOSFETs are almost the same. This implies that power

ICs with a vertical DMOS output will be replaced by power ICs with a lateral DMOS output, if current capacity is not large—for example, less than 10 A.

High-side switching operation is an important function in automotive applications, especially in case of H-bridges for motor control. The on-resistance of conventional junction-isolated high-voltage MOSFETs, shown in Figure 7.26a, is significantly influenced by the source-to-substrate bias [26], because a large part of the n-type epilayer is depleted. However, in SOI MOSFETs as shown in Figure 7.28, the drift layer is not depleted, but a hole inversion layer is formed on the buried oxide. Thus, the substrate bias influence of SOI LDMOS is small [26].

Figure 7.29 shows a 60 V DMOS in 2-µm-thick p-type SOI. The fabrication process is completely compatible with the CMOS process. The threshold voltage is controlled by the channel implant. The experimentally obtained specific on-resistance of 60 V LDMOS is 100 mΩ mm2. The developed power MOSFET is completely free from substrate bias influence [27]. This is because the hole accumulation layer is induced on the buried oxide, leaving the n-drift layer unchanged. These results indicate that this device can be used for a high-side switch without on-resistance increase.

Adaptive Resurf

Figure 7.30a shows a cross-sectional view of a typical Resurf LDMOS on p-epi layer with n+ buried layer. The Resurf structure is often used to increase the static breakdown voltage and to reduce the on-resistance. Figure 7.31a shows a typical I–V curve of a Resurf LDMOS. The on-resistance is 15.7 mΩ mm2 at the gate voltage, Vg, of 5 V. The static breakdown voltage is 30.2 V. The device breakdown voltage decreases to 13.9 V when the device is operating at the gate voltage of 5 V. The breakdown voltage, when the device is in conduction state, is called as on-state breakdown voltage.

The reason why the on-state breakdown voltage is degraded is that the net effective positive charge is reduced by the existence of a large amount of negative electron charges in the Resurf layer due to a large

drain current. Figure 7.32a shows the space-charge distribution when the junction breakdown occurs for 0 V and 5 V gate voltages. These figures indicate that the positive space charge of the n-Resurf region is compensated by the negative charge of electron current flow when the gate voltage is 5 V. Thus, the net positive charge in the depleted Resurf layer deviates markedly from the optimized value, when the device is on-state. The net positive Resurf charge ρnet under a drain current of ID is expressed by

where ρResurf dose denotes the original Resurf dose and vs the electron saturation velocity.

Figure 7.30b shows 20 V LDMOS with adaptive Resurf [28]. The structure is characterized by the additional second n-Resurf layer, whose impurity dose is chosen to be higher than the first Resurf layer. As the impurity dose in the second n-Resurf layer increases, the on-state breakdown voltage increases. Optimum dose for the second n-Resurf is ρResurf dose + ID/qvs, which provides optimum Resurf charge, ρResurf dose, when the drain current, ID , flows.

The adaptive Resurf concept is that the optimum positive Resurf charge is always provided either by the first or the second Resurf layer, depending on the current level. Figure 7.31b shows the calculated I–V curve for the LDMOS adopting the optimized two-step adaptive Resurf layers. The high breakdown voltage of 21.8 V is still retained at a gate voltage of 5 V. Figure 7.32b shows the space-charge distribution when the breakdown occurs for 0 and 5 V gate voltages. These figures indicate that the positive space charge of the first n-Resurf region is compensated by the negative charge of current flow when the gate voltage is 5 V, but the positive space charge of the second n-Resurf region remains. This positive space- charge region sustains a high on-state breakdown voltage.

Metal Wiring Resistance

The on-resistance of LDMOS itself becomes significantly small as the design rule becomes finer and finer as shown in Figure 7.10. If the device on-resistance becomes comparable to that of the sheet resistance of metal layer, the metal wiring resistance cannot be ignored. For example, the sheet resistance of 1-µm-thick aluminum layer is 28 mΩ/ . The typical aluminum layer thickness of conventional fine CMOS process is less than 1 µm. Figure 7.33 shows calculated LDMOS on-resistance of 1 mm2 device area as a function of second metal layer thickness with aluminum layer width, W, as a parameter. The source and drain aluminum layer widths are defined in Figure 7.34. The first aluminum layer thickness is assumed to be 1 µm for all the calculated cases. The total number of the second metal layers are chosen so that the total second metal layer width becomes 1 mm. The overall LDMOS on-resistance depends significantly on the metal thickness and its layout. The pure silicon on-resistance of the calculated device is 40 mΩ mm2. It is concluded that the 5 µm or much thicker metal layer is necessary to realize less than 50 mΩ on-resistance devices. Today, a thick copper metal layer is often utilized to realize low on-resistance LDMOS from this viewpoint.

Lateral IGBTs on SOI

IGBTs are suitable for high-voltage medium-current power ICs because of large current capability, as shown in Figure 7.35. IGBT can be recognized as a pnp transistor driven by an n-channel MOSFET for a first-order approximation. Lateral IGBTs can be fabricated by conventional CMOS compatible processes. The switching speed of bipolar power devices is conventionally controlled by introduction of a lifetime killer. However, lifetime control process is not compatible with conventional CMOS process. There are two ways to control switching speed of power devices. One way is to use thin SOI layers. The switching speed of IGBTs improves as the SOI thickness decreases, because carrier lifetime is effectively decreased by the influence of large carrier recombination at the silicon dioxide interfaces [29]. The other way is to reduce emitter efficiency of the p+ drain or collector. The effective methods are (1) emitter short, (2) low-dose emitter [30], (3) high-dose n buffer, and (4) forming an n+ layer in the p+ emitter [31].

Figure 7.36 shows a cross section of large current lateral IGBTs. Large current capability has been realized by adopting multiple surface channels. Figure 7.37 shows typical current voltage curves of the

multichannel LIGBT. The current is an exponential function of the drain bias (collector bias) for low- voltage range. The current voltage curves seem to have 0.8 V off-set voltage just like a diode. Typical switching speed of the developed LIGBTs is 300 ns.

It is extremely important to increase operating current density of LIGBTs to reduce chip size. This is because output devices occupy most of the chip area and the cost of the power ICs deeply depends on the size of the power devices. The current density of the developed LIGBT is 175 A/cm2 for 3 V forward voltage.