Power IC Technologies:High-Voltage Technology

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High-Voltage Technology

It is quite important to realize a high breakdown voltage in an integrated device structure. There are two major techniques to realize high-voltage lateral devices. These are field plate and Resurf technique.

Field Plate

It is ideal if one-dimensional (1-D) pn junction breakdown voltage is realized in an actual planar pn junction, which is formed by thermal impurity diffusion. Actual planar pn junctions consist of cylindrical junctions and spherical junctions near the surface. Generally, breakdown voltage of cylindrical or spher- ical junctions is significantly lower than that of ideal 1-D planar junction, if the junction curvature is small. A field plate is a simple and frequently used technique to increase the breakdown voltage of actual planar junctions. Figure 7.13 shows an example. Field plates, placed on the thick field oxide, induce depletion layers underneath themselves. The curvature of the formed depletion layers can be reduced with the induced depletion layers, relaxing the curvature effects by the field plate.

Resurf Technology

Resurf technique was originally proposed in 1979 [14] as a method to obtain a high breakdown voltage in conventional JI structure. Figure 7.14 shows a high-voltage structure, where depletion layer develops in the p substrate and n-epitaxial layer. If the epilayer impurity dose, Qc, is high, premature breakdown occurs before n-epi layer is fully depleted. If the impurity dose in the epilayer is optimized, the epilayer

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is just completely depleted when breakdown occurs. The achieved breakdown voltage is very high because depletion layer is sufficiently thick both in lateral and vertical direction. The important point is that the total charge, Qc, in the epilayer is chosen so that the value satisfies the equation

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where Ec denotes critical electric field in silicon (3 × 105 V/cm). This charge can be depleted just when the electric field becomes Ec and the junction breakdown occurs. In other words, the epilayer is completely depleted just when the breakdown occurs, if the total epilayer dose is Qc /q, which is approx- imately 2 × 1012 cm–2.

If the n-epi layer dose, Qc, is excessively low, the epilayer is completely depleted before the vertical electric field reaches the critical field. The premature breakdown again occurs in this case, as the surface electric field exceeds the critical value at the edge of the n+ layer.

High-Voltage Metal Interconnection

In high-voltage power ICs, there must be interconnection metal layers crossing high-voltage junctions. These high-voltage interconnection layers may cause degradation of breakdown voltage of high-voltage devices. These problems are often solved with a thicker insulator layer underneath the interconnection layers. However, special means are required if the breakdown voltage is over 400 V.

Figure 7.15 shows one of the methods to shield the influence of metal interconnection layers on the underlying devices. A spiral-shaped high-resistance polysilicon layer, connecting source and drain elec- trodes, effectively shields the influence of the interconnection layer on the depletion layer [22]. This is because the potential of high-resistance polysilicon layer is determined by small leakage current.

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Another typical example is multiple floating field plates. The cross-section of the structure is similar to Figure 7.15. The difference is that the polysilicon forms multiple closed rings, which are electrically isolated from each other. Multiple floating field plates also prevent the breakdown voltage reduction due to metal interconnection.

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