Microelectronics Packaging:Package Parameters

Package Parameters

A successful package design will satisfy all given application requirements at an acceptable design, manufacturing, and operating expense. As a rule, application requirements prescribe the number of logic circuits and bits of storage that must be packaged, interconnected, supplied with electric power, kept within a proper temperature range, mechanically supported, and protected against the environment. Thus, packages are designed to provide semiconductor IC with signal and power distribution, physical support, and chemical protection against the environment. Besides, the package is also designed to provide the capability to remove heat produced by the chips and to enhance the reliability of the packaging structures.

To perform these functions successfully, package designers start with a fundamental concept and, using principles of engineering, material science, and processing technology, create a design that is low cost and encompasses low lead capacitance and inductance, low thermal resistance, safe stress levels, material compatibility, seal integrity, high reliability, and ease of manufacture.

Given that cost and performance are the primary concerns in electronic packaging, it is important to examine the factors which relate performance and cost to packaging technology choices. Factors that must be considered include manufacturability, reliability, signal integrity, size, weight, power consumption, heat dissipation, etc. Conflicts among these multiple criteria are common. The design process involves many tradeoff analyses and the optimization of conflicting requirements [1,2,7,8] .

While designing the package for an application, it is important to have the module defined before committing to a specific package design. The following parameters are considered.

Number of Terminals

The establishment of and adherence to good chip design rules are essential to achieving high yields in IC package assembly. The total number of terminals at packaging interfaces is a major cost factor. Signal interconnections and terminals constitute the majority of conducting elements, especially in low-cost packaging. Other conductors supply power and provide ground or other reference voltages.

Circuit partitioning and an appropriate net topology are essential to minimize the reflection noise in the packaging of high-speed circuitry and multichip modules. The number of terminals supporting a group of circuits is strongly dependent on the function of this group. With memory ICs, the smallest pinout can be obtained because the stream of data can be limited to a single bit. Exactly the opposite is the case with groups of logic circuits owing to a random partitioning of a computer. The pinout requirement is one of the key driving parameters for all levels of packaging [1–3,9,10].

Electrical Design Considerations

The two primary electrical functions of an electronic package are to deliver power to the circuits and to carry electrical signals from one circuit to another. Hence, the major electrical design objectives in electronic packaging are to maintain signal fidelity in signal paths and to minimize noise generation in electrical power conductors while minimizing the cost. High-speed systems have unique requirements for packaging technology as a result of the relatively short wavelength of the electromagnetic energy and the circuit components must be considered as distributed elements rather than as lumped elements.

High-speed digital design, in contrast to digital design at low speeds, emphasizes the behavior of passive circuit elements such as wires, circuit boards, and so on. At low speeds, passive circuit elements are just part of a product’s packaging. At higher speeds, as a signal propagates through the package, it is degraded owing to reflections and line resistance (see Table 8.3). Controlling the resistance and the inductance

associated with the power and ground distribution paths to combat ground bounce and the simultaneous switching noise is essential. Besides, controlling the impedance environment of the signal distribution path in the package to mitigate the reflection-related noise is important. Reflections cause an increase in the transition time and may split the signal into two or more pulses with the potential of causing erroneous switching in the subsequent circuit and thus malfunctioning of the system. Controlling the capacitive coupling between signal traces in the signal distribution path to reduce cross talk is also important [11–14]. Increased speed of the devices demands that package bandwidth be increased to reduce undue distortion of the signal. All these criteria are related through geometric variables such as conductor cross section and length, dielectric thickness, and the dielectric constant of the packaging body. These problems are usually handled with transmission line theory [15–17].

Thermal Design Considerations

Reliability at all levels of packaging is directly related to operating temperature. Higher operating tem- peratures accelerate various failure mechanisms such as creep, corrosion, and electromigration. In addition, an electronics packaging is a composite structure. Owing to the thermal expansion mismatch of different parts of the packaging, thermal stresses and strains can occur inside a packaging system while it is being manufactured and while it is being used [18,19]. The demands to reduce packaging signal delay and increase packaging density have made chip power dissipation a major concern. Thus, thermal (temperature, stress, and strain) management is vital for microelectronics packaging designs and analyses.

In a simplistic heat transfer model of a packaged chip, the heat is transferred from the chip to the surface of the package by conduction and from the package surface to the ambient by convection and radiation. Figure 8.3 exhibits the heat transfer from a region in the silicon device to the ambient for a ball grid array (BGA) package. The total thermal resistance Rθ ja from the junction to the ambient is obtained from the resistance network (see Figure 8.3[c])

The junction temperature Tj, assuming a power dissipation of θchip is

in analogy with electric circuits. If there are parallel paths for heat flow, the thermal resistances are combined in exactly the same manner as electrical resistors in parallel.

Typically, the temperature difference between the case and ambient is small, and hence radiation can be neglected. It is generally recommended to keep the junction temperature below 115°C to ensure proper electrical performance and a reasonable lifetime.

The conductive thermal resistance is mainly a function of package materials and geometry. The temperature dependence of materials selected in design must be considered when high power is required. The junction temperature Tj depends on package geometry, package orientation in the application, and the conditions of the ambient in the operating environment. Heat sink is used for getting rid of the heat of the environment by convection and radiation. Because of all the many heat transfer modes occurring in a finned heat sink, the accurate way to obtain the exact thermal resistance of the heat sink would be to measure it. However, most heat sink manufactures today provide information about their extrusions concerning the thermal resistance per unit length. Other cooling techniques such as use of heat pipes, thermoelectric cooling, and microchannel cooling are available to the thermal designers [20–22]. Thermal expansion caused by heating up the packaging structure is not uniform—it varies in accordance with the temperature gradient at any point in time and with the mismatches in the thermal coefficient of expansion. Mechanical stresses result from these differences and are one of the contributors to the finite lifetime and the failure rate of any packaging structure.

The information required for package design includes physical chip size, chip foot print (i.e., inline/staggered pads and pad pitch for wirebond die, bump pitch, and number of rows for flip chip die), die netlist (signals, power, and ground), type of package (ceramic, laminate, or plastic), package thermal and electrical performance requirements, footprint and pitch for second-level connections

(signal, power, and ground assignment), and type of substrate for second-level packaging. The selection criteria for a package design are cost, maximum die-step size, electrical performance, and thermal performance.

Reliability

The package should have good thermomechanical performance for better reliability. The causes for the failure of an electronic product may be thermal, mechanical, electrical, chemical or a combination of these, but all failures are electrical failures eventually. To ensure that the electronics packaging will be reliable over an extended period of time, three approaches need to be followed: (1) understand, identify the major failure mechanisms of packaging for respective applications, and design the pack- aging for reliability [23] (see Table 8.4); (2) careful control of the packaging process to manufacture the packaging for reliability [24] (see Table 8.5); and (3) conduct accelerated test on the packaging for reliability [25,26].

Testability

Implicit in reliability considerations is the assumption of a flawless product function after its initial assembly. However, a zero-defect manufacturing is rarely practiced because of the high costs and possible loss of competitive edge owing to conservative dimensions, tolerances, materials, and process choices. So, two types of tests are employed to assess the reliability of the packages, namely, reliability test and functional test. The acceleration factor, AF, an important term in the subject of reliability test is the ratio of the degradation or failure time at temperature T1 relative to that at an elevated, accelerated-test temperature T2. In using the AF concept it is assumed that the mechanism of damage does not change

Minimize stress, defects, and/or flaws Minimize stress and use better materials Improve adhesion

Apply shielding layer

Improve circuit design, use ground tools etc. Lower voltage and improve oxide layer Reduce current density

Use better material

Minimize stress/strain/temperature and use alternate materials, geometry, and dimensions Minimize stress and use refractory materials Minimize stress and use harder materials Minimize stress Reduce current density and use alternate metal (such as Cu) Improve process and use metal barrier layer Provide sealing and encapsulation Lower temperature and use diffusion barrier Increase thickness and reduce humidity

in the accelerated-test process. The AF values obtained from accelerated testing under some set of stress- test conditions are incorporated into reliability functions that are valid under use conditions. The stress includes temperature, voltage, current, and humidity, taken singly or in combination. The Arrhenius equation is often used to evaluate the activation energy for degradation. However, the Arrhenius model applies only to thermally activated processes. It is invalid for facture caused by mechanisms such as ESD, mechanical shock, etc. [27,28]. Besides, even for the thermally activated degradation process, it is difficult to isolate and characterize individual damage mechanisms when an admixture or distribu- tion of activation energies may exist [29]. Functional test is used to determine whether a particular function of the board is working properly by toggling the circuitry through its legal states or conditions. Functional test is necessary in circuits to detect all possible faults that could prevent proper circuit operation. Design for test minimizes the cost and maximizes the success and value of the test process. New ESD test methods and equipment are required to comprehend the increasing pincount and shrinking interconnect pitch.