Microelectronics Packaging:Future Trends

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Future Trends

Packaging needs are driven as much by market application requirements as by silicon technology. The package cost has to follow the die cost reduction curve. As the complexity of package technology continues to increase, new materials will be needed to meet design, performance, and cost challenges. Efficient thermal management is a must for high speed dies. Significant engineering development will be needed for power increases at each technology generation.

Environmental concerns will continue to impact the selection/design of packaging materials/processes such as materials and surface finishes for lead-free solder assembly and for halogen-free materials [61,62]. For the next-generation substrate, both chip-in-substrate (i.e., embedded active IC devices) packaging technology [63–66] and packaging for flexible applications [67,68] are two important fields. Bumpless area array technologies will be needed to further reduce the package parasitics. System-on-package (SoP) is an emerging concept for highly integrated multifunctional system. SoP may overcome both the com- puting limitations and integration limitations of system-on-chip (SoC), system-in-package (SiP), MCM, and traditional packaging [61,69–71].

Packaging design and fabrication are increasingly important to system applications. Consideration of factors affecting waveform integrity for both power and signal (i.e., timing, cross talk, and ground bounce) will affect device layout on the chip, chip layout on the package, and interconnect. Package designs no longer can be developed independently of the chip and system; they must be considered concurrently as part of the overall system design. Chip–package–substrate codesign is the trend for high-performance systems.

System-level design capability is a critical issue. An integrated design environment of physical, electrical, thermal, thermo-mechanical, chip, package, and system design needs to be evolved. Coordinated design tools and simulators to address chip, package, and substrate codesign are required to manage the complexity of packaging that is being pushed to its performance limits.

Conventional surface mount packages will dominate in the region of low pin count and low clock frequency. BGA and chip-scale packages will be used for medium pin counts. Bare chip solutions, with high density and good electrical properties, could be very competitive with packaged solutions. However, bare chip solutions have a reliability versus cost tradeoff. Interconnection methods which offer direct pathways between chips to improve the performance of electronic products with minimal disruption to manufacturing infrastructure are needed to meet performance and cost challenges [72].

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