Microelectronics Packaging:Die Attachment Techniques

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Die Attachment Techniques

There are various bonding techniques for the first-level packaging. The three most widely used die attachment techniques are wire bonding, TAB, and solder bump bonding (see Figure 8.7).

Wire Bonding

Wire bonding is a technique to provide electrical interconnections from the terminals on a chip circuit to those on a chip carrier circuit by using a fine wire. This substrate may simply be the ceramic base of a package or another chip. The common materials used are gold and aluminum. The main advantage of wire-bonding technology is its low cost; but it cannot provide large I/O counts, and it needs large bond pads to make connections. The connections have relatively poor electrical performance.

Tape-Automated Bonding

In TAB technology, a chip is placed on a polymer tape with interconnection patterns. The tape is positioned above the “bare die” so that the metal tracks on the polymer tape correspond to the bonding sites on the die. TAB technology provides several advantages over wire bonding technology. It requires a smaller bonding pad, smaller on-chip bonding pitch, and a decrease in the quantity of gold used for bonding. It has better electrical performance, lower labor costs, higher I/O counts and lighter weight, greater densities, and the chip can be attached in a face-up or face-down configuration. However, TAB technology includes time and cost of designing and fabricating the tape and the capital expense of the TAB bonding equipment. Besides, each die must have its own tape patterned for its bonding configuration. Thus, TAB technology has been limited to high-volume applications.

Solder Bump Bonding

In solder bump-bonding processes, solder bumps are bonded to the pads of the semiconductor chip, the chip is flipped over, the solder bumps are aligned with the contact pads on the substrate and reflowed in a furnace to establish the bonding between the die and the substrate. This technology provides electrical

Microelectronics Packaging-0127

connections with minute parasitic inductances and capacitances. In addition, the contact pads are dis- tributed over the entire chip surface rather than being confined to the periphery. As a result, the silicon area is used more efficiently, the maximum number of interconnects is increased, and signal intercon- nections are shortened. But this technique results in poor thermal conduction, difficult inspection of the solder bumps, and possible thermal expansion mismatch between the semiconductor chips and the substrate. Underfill epoxy encapsulant is used to reduce the effect of thermal expansion mismatch between the silicon chip and the organic substrate. The underfill reduces the stresses and strains in the flip-chip solder joints and redistributes the stresses and strains over the entire chip area that would otherwise be increasingly concentrated near the corner solder joints of the chip. Thus, the reliability of the flip-chip solder joints is enhanced [47,48].

Other bonding techniques

There are other bonding techniques such as sea of leads (SoL)-compliant interconnect technique [49], stud bump bonding [37], surface-activated bonding [50], and bonding with conductive adhesives or metal bumps [51,52].

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