Low Power Microarchitecture Techniques:Conclusions and Future Research Directions

Conclusions and Future Research Directions

When it comes to performance, superscalar processor designers have always been the last to accept a possible compromise. As intended for applications, where raw performance is the primary target, the last bit of potential efficiency is usually squeezed from each architectural design. Traditionally, power

dissipation issues have been addressed mainly at the technology level, through lower supply voltages, smaller transistors, SOI technology, better packaging, etc. Nevertheless though, power dissipation has lately become one of the design constraints for modern processors, and thus the microarchitecture designer must now take power requirements into consideration as well. We have already reached the limits of our capabilities for economical cooling and power delivery, and future microarchitecture designs will have to fit within a roughly similar power envelope.

This reality makes power consumption a first rate design challenge, and future microprocessors will have to spend less power per instruction to become economically viable. While various DVS techniques can lower power consumption in cases where high performance is not required, this is primarily a solution for portable devices. In general, processors need to become more power efficient, performing less- speculative work, which is eventually thrown out and utilizing less logic real estate for performing useful work. In this respect, techniques like the EC help in reducing the switched capacitance per committed instruction. By concentrating the activity in the back-end portion of the pipeline, this method allows the entire front-end of the processor to be gated off to limit the dynamic power consumption.

A different challenge comes from the increased variability associated with smaller process technologies. Since it becomes harder to make chip-wide decisions without sacrificing performance and power effi- ciency, local solutions will start to gain importance. The GALS design methodology fits very well into this trend, allowing logic islands to communicate asynchronously on a per-need basis. Each such island can be designed and optimized separately, limiting the impact of process variability on the entire chip. Finally, the decreasing feature sizes translate into smaller transistor junctions and thinner isolator layers. Such transistors leak current even when they do not switch state, and this leakage power has already become a problem for the existing process technologies. While dynamic power consumption can be limited by clock gating, this static power is consumed by all transistors of the design, even when they do not perform any work at all. Depending on the type of logic block, there are several solutions for dealing with this problem (see Section 19.3.3), but all of them have drawbacks and tend to affect performance. Since the leakage current increases exponentially with each new process technology, static

power consumption is gradually gaining the same importance as the dynamic power.