High-Frequency Amplifiers:Current Feedback OP-AMP (CFOA).

Introduction

As the operating frequency of communication channels for both video and wireless increases, there is an ever-increasing demand for high-frequency ampliﬁers. Furthermore, the quest for single-chip inte- gration has led to a whole new generation of ampliﬁers predominantly geared toward CMOS very large- scale integration (VLSI). In this chapter we will focus on the design of high-frequency ampliﬁers for potential applications in the front-end of video, optical, and RF systems. Figure 24.1 shows for example, the architecture of a typical mobile phone transceiver front-end. With channel frequencies approaching the 2 GHz range coupled with demands for reduced chip size and power consumption, there is an increasing quest for VLSI at microwave frequencies. The shrinking feature size of CMOS has facilitated the design of complex analog circuits and systems in the 1–2 GHz range, where more traditional low- frequency lumped circuit techniques are now becoming feasible. Since the ampliﬁer is the core component in such systems, there has been an abundance of circuit design methodologies for high-speed, low-voltage, low-noise, and low-distortion operation.

This chapter will present various ampliﬁer designs that aim to satisfy these demanding requirements. In particular we will review, and in some cases present new ideas for power amps, low-noise ampliﬁers (LNAs), and transconductance cells, which form core building blocks for systems such as in Figure 24.1. Section 24.2 begins by reviewing the concept of current feedback, and shows how this concept can be employed in the development of low-voltage, high-speed, constant-bandwidth CMOS ampliﬁers. The next two sections of the chapter focus on ampliﬁers for wireless receiver applications, investigating performance requirements and design strategies for optical receiver ampliﬁers (Section 24.3) and high- frequency LNAs (Section 24.4). Section 24.5 considers the design of ampliﬁers for the transmitter side, and in particular the design and feasibility of class E power amps is discussed. Finally, Section 24.6 reviews a very recent low-distortion ampliﬁer design strategy termed “log-domain”, which has shown enormous potential for high-frequency, low-distortion tunable ﬁlters.

Current Feedback OP-AMP (CFOA)

CFOA Basics

The operational ampliﬁer (op-amp) is one of the most fundamental building blocks of analog circuit design [1,2]. High-performance signal-processing functions such as ampliﬁers, ﬁlters, and oscillators can be readily implemented with the availability of high-speed, low-distortion op-amps. In the last decade, the development of complementary bipolar technology has enabled the implementation of single-chip video op-amps [3–7]. The emergence of op-amps with nontraditional topologies such as the CFOA has improved the speed of these devices even further [8–11]. CFOA structures are well known for their ability to overcome (to a ﬁrst-order approximation) the gain-bandwidth trade-off and slew rate limitation that characterizes traditional voltage feedback op-amps [12].

Figure 24.2 shows a simple macromodel of a CFOA, along with a simpliﬁed circuit diagram of the basic architecture. The topology of the CFOA differs from the conventional voltage feedback op-amp (VOA) in two respects. First, the input stage of a CFOA is a unity-gain voltage buffer connected between the inputs of the op-amp. Its function is to force Vn to follow Vp, very much like a conventional VOA does via negative feedback. In the case of the CFOA, because of the low-output impedance of the buffer, current can ﬂow in or out of the inverting input, although in normal operation (with negative feedback) this current is extremely small. Second, a CFOA provides a high open-loop transimpedance gain Z(jw), rather than open-loop voltage gain as with a VOA. This is shown in Figure 24.2, where a current-controlled current source senses the current IINV delivered by the buffer to the external feedback network, and copies this current to a high-impedance Z(jw). The voltage conveyed to the output is given by

When the negative feedback loop is closed, any voltage imbalance between the two inputs owing to some external agent, will cause the input voltage buffer to deliver an error current IINV to the external network. This error current IINV I1 -I2 Iz is then conveyed by the current mirrors to the impedance Z(jw), resulting in an ouput voltage as given by Eq. (24.1). The application of negative feedback ensures that VOUT will move in the direction that reduces the error current IINV and equalizes the input voltages.

We can approximate the open-loop dynamics of the CFOA as a single pole response. Assuming that the total impedance Z(jw) at the gain node is the combination of the output resistance of the current mirrors Ro in parallel with a compensation capacitor C we can write

where wo = 1/RoC represents the frequency, where the open-loop transimpedance gain is 3 dB down from its low frequency value Ro. In general Ro is designed to be very high in value.

Eq. (24.6) indicates that the closed-loop bandwidth does not depend on the closed-loop gain as in the case of a conventional VOA, but is determined by the feedback resistor RF . Explaining this intuitively, the current available to charge the compensation capacitor at the gain node is determined by the value of the feedback resistor RF and not Ro , provided that Ro >> RF . So once the bandwidth of the ampliﬁer is set via RF , the gain can be independently varied by changing RG. The ability to control the gain independently of bandwidth constitutes a major advantage of CFOA over conventional VOA.

The other major advantage of the CFOA compared to the VFOA is the inherent absent of slew rate limiting. For the circuit of Figure 24.2, assume that the input buffer is very fast and thus a change in voltage at the noninverting input is instantaneously converted in to the inverting input. When a step .1VIN is applied to the noninverting input, the buffer output current can be derived as

Eq. (24.8) indicates an exponential output transition with time constant t = RFC. Similar to the small- signal frequency response, the large-signal transient response is governed by RF alone regardless of the magnitude of the closed-loop gain. The absence of slew rate limiting allows for faster settling times and eliminates slew rate-related nonlinearities.

In most practical bipolar realizations, Darlington-pair transistors are used in the input stage to reduce input bias currents, which makes the op-amp somewhat noisier and increases the input offset voltage. This is not necessary in CMOS realizations owing to the inherently high MOSFET input impedance. However, in a closed-loop CFOA, RG should be much larger than the output impedance of the buffer. In bipolar realizations it is fairly simple to obtain a buffer with low output resistance, but this becomes more of a problem in CMOS owing to the inherently lower gain of MOSFET devices. As a result, RG typically needs to be higher in a CMOS CFOA than in a bipolar realization, and consequently RF needs to be increased above the value required for optimum high-frequency performance. Additionally, the fact that the input buffer is not in the feedback loop imposes linearity limitations on the structure, especially if the impedance at the gain node is not very high. Regardless of these problems, CFOAs exhibit excellent high-frequency characteristics and are increasingly popular in video and communications applications [13].

The following sections outline the development of a novel low-output impedance CMOS buffer, which is then employed in a CMOS CFOA to reduce the minimum allowable value of RG.

CMOS Compound Device

A simple PMOS source follower is shown in Figure 24.4. The output impedance seen looking into the source of M1 is approximately Zout = 1/gm, where gm is the small-signal transconductance of M1. To increase gm the drain current of M1 could be increased, which leads to an increased power dissipation. Alternatively, the dimensions of M1 can be increased, resulting in additional parasitic capacitance and hence an inferior frequency response. Figure 24.5 shows a conﬁguration, which achieves a higher transconductance than the simple follower of Figure 24.4 for the same bias current [11]. The current of M2 is fed back to M1 through the a:1 current mirror. This conﬁguration can be viewed as a compound transistor, whose gate is the gate of M1 and whose source is the source of M2. The impedance looking into the compound source can be approximated as Zout = (gm1 - agm2)/(gm1gm2), where gm1 and gm2 represent the small-signal transconductance of M1 and M2, respectively. The output impedance can be made small by setting the current mirror transfer ratio a = gm1/gm2.

The p-compound device is practically implemented as in Figure 24.6. To obtain a linear voltage transfer function from node 1 to 2, the gate-source voltages of M1 and M3 must cancel. The current mirror (M4–M2) acts as NMOS–PMOS gate-source voltage matching circuit [14] and compensates for the difference in the gate-source voltages of M1 and M3, which would normally appear as an output offset. DC analysis, assuming a square law model for the MOSFETs, shows that the output voltage exactly follows the input voltage. However, in practice, channel length modulation and body effects preclude exact cancellation [15].

Buffer and CFOA Implementation

The CFOA shown in Figure 24.7 has been implemented in a single-well 0.6 mm digital CMOS process [11]; the corresponding layout plot is shown in Figure 24.8. The chip has an area of 280 mm X 330 mm and a power dissipation of 12 mW. The ampliﬁer comprises two voltage followers (input and output) connected by cascoded current mirrors to enhance the gain node impedance. A compensation capacitor (Cc = 0.5 pF) at the gain node ensures adequate phase margin and thus closed-loop stability. The voltage followers have been implemented with two compound transistors, p type and n type, in a push–pull arrangement. Two such compound transistors in the output stage are shown shaded in Figure 24.7. The input voltage follower of the CFOA was initially tested open loop, and measured results are summarized in Table 24.1. The load is set to 10 kW//10 pF except where mentioned otherwise, 10 kW being a limit imposed by overall power dissipation of the chip. Intermodulation distortion was measured with two tones separated by 200 kHz. The measured output impedance of the buffer is given in Figure 24.9. It remains below 80 W up to a frequency of about 60 MHz, when it enters an inductive region. A maximum impedance of 140 W is reached around 160 MHz. Beyond this frequency, the output impedance is dominated by parasitic capacitances. The inductive behavior is characteristic of the use of feedback to reduce output impedance and can cause stability problems when driving capacitive loads. Small-signal analysis (summarized in Table 24.2) predicts a double zero in the output impedance [15].

Decreasing the value of factor G in Table 24.2 will not only reduce the output impedance, but will also move the double zero to lower frequencies and intensify the inductive behavior. The principal trade- off in this conﬁguration is between output impedance magnitude and inductive behavior. In practice, the output impedance can be reduced by a factor of 3 while still maintaining good stability when driving capacitive loads. Figure 24.10 shows the measured frequency response of the buffer. Given the low-power dissipation, excellent slew rates have been achieved (Table 24.2).

After the characterization of the input buffer stage, the entire CFOA was tested to conﬁrm the suitability of the compound transistors for the implementation of more complex building blocks. Open-loop

transimpedance measurements are shown in Figure 24.11. The bandwidth of the ampliﬁer was measured at gain settings of 1, 2, 5, and 10 in a noninverting conﬁguration, and the feedback resistor was trimmed to achieve maximum bandwidth at each gain setting separately. CFOA measurements are summarized in Table 24.3, loading conditions are again 10 kW//10 pF.

Figure 24.12 shows the measured frequency response for various gain settings. The bandwidth remains constant at 110 MHz for gains of 1, 2, and 5 consistent with the expected behavior of a CFOA. The bandwidth falls to 42 MHz for a gain of 10 owing to the ﬁnite output impedance of the input buffer stage which serves as the CFOA inverting input. Figure 24.13 illustrates the step response of the CFOA driving a 10 kW//10 pF load at a voltage gain of 2. It can be seen that the inductive behavior of the buffers has little effect on the step response. Finally, distortion measurements were carried out for the entire CFOA for gain settings 2, 5, and 10 and are summarized in Table 24.3. HD2 levels can be further improved by employing a double-balanced topology. A distortion spectrum is shown in Figure 24.14; the onset of HD3 is owing to clipping at the test conditions.

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