High-Frequency Amplifiers:Applications of High-Q Resonators in IF-Sampling Receiver Architectures

Applications of High-Q Resonators in IF-Sampling Receiver Architectures

Transconductance-C (gm-C) filters are currently the most popular design approach for realizing continuous-time filters in the intermediate frequency range in telecommunications systems. This section will consider the special application area of high-Q resonators for receiver architectures employing IF-sampling.

IF Sampling

A design approach for contemporary receiver architectures that is currently gaining popularity is IF digitization, whereby low-frequency operations such as second mixing and filtering can be performed more efficiently in the digital domain. A typical architecture is shown in Figure 24.31. The IF signal is digitized, mixed with the quadrature phases of a digital sinusoid, and lowpass filtered to yield the quadrature baseband signals. Since processing takes place in the digital domain, I/Q mismatch problems are eliminated. The principal issue in this approach, however, is the performance required from the A/D converter. Noise referred to the input of the A/D must be very low so that selectivity remains high. At the same time, the linearity of the A/D must be high to minimize corruption of the desired signal through intermodulation effects. Both the above requirements should be achieved at an input bandwidth commensurate with the value of the IF frequency, and at an acceptable power budget.

Oversampling has become popular in recent years because it avoids many of the difficulties encountered with conventional methods for A/D and D/A conversion. Conventional converters are often difficult to implement in fine-line VLSI technology, because they require precise analog components and are very sensitive to noise and interference. In contrast, oversampling converters trade off resolution in time for resolution in amplitude, in such a way that the imprecise nature of the analog circuits can be tolerated. At the same time, they make extensive use of digital signal-processing power, taking advantage of the fact that fine-line VLSI is better suited for providing fast digital circuits than for providing precise analog circuits. Therefore, IF-digitization techniques utilizing oversampling Sigma–Delta modulators are very well suited to modern submicron CMOS technologies, and their potential has made them the subject of active research.

Most Delta–Sigma modulators are implemented with discrete-time circuits, switched-capacitor (SC) implementations being by far the most common. This is mainly due to the ease with which monolithic SC filters can be designed as well as the high linearity which they offer. The demand for high speed SD oversampling A/D converters, especially for converting bandpass signals, makes it necessary to look for a technique that is faster than SC. This demand has stimulated researchers to develop a method for designing continuous-time DS A/Ds. Although continuous-time modulators are not easy to integrate, they possess a key advantage over their discrete-time counterparts. The sampling operation takes place inside the modulator loop, making it is possible to “noise-shape” the errors introduced by sampling, and provide a certain amount of anti-aliasing filtering at no cost. On the other hand, they are sensitive to memory effects in the D/As and are very sensitive to jitter. They must also process continuous-time signals with high linearity. In communications applications, meeting the latter requirement is complicated by the fact that the signals are located at very high frequencies.

As shown in Figure 24.32, integrated bandpass implementations of continuous-time modulators require integrated continuous-time resonators to provide the noise shaping function. The gm-C approach of realizing continuous-time resonators offers advantages of complete system integration and total design freedom. However, the design of CMOS high-Q high-linearity resonators at the tens of megahertz is very challenging. Since the linearity of the modulator is limited by the linearity of the resonators utilized, the continuous-time resonator is considered to be the most demanding analog subblock of a bandpass

Linear Region Transconductor Implementation

The implementations of fully integrated high-selectivity filters operating at tens to hundreds of megahertz provides benefits for wireless transceiver design, including chip area economy and cost reduction. The main disadvantages of on-chip active filter implementations when compared to off-chip passives include increased power dissipation, deterioration in the available dynamic range with increasing Q, and Q and resonant frequency integrity (because of process variations, temperature drifts, and aging, automatic tuning is often unavoidable especially in high-Q applications). The transconductor-capacitor (Gm-C) technique is a popular technique for implementing high-speed continuous-time filters and is widely used in many industrial applications [50]. Because Gm-C filters are based on integrators built from an open- loop transconductance amplifier driving a capacitor, they are typically very fast, but have limited linear dynamic range. Linearization techniques which reduce distortion levels can be used, but often lead to a compromise between speed, dynamic range, and power consumption.

As an example of the trade-offs in design, consider the transconductor shown in Figure 24.33. This design consists of a main transconductor cell (M1, M2, M3, M4, M10, M11, and M14) with a negative resistance load (M5, M6, M7, M8, M9, M12, and M13). Transistors M1 and M2 are biased in the triode region of operation using cascode devices M3 and M4 and determine the transconductance gain of the cell. In the triode region of operation the drain current versus terminal voltage relation can be approximated (for simple hand calculations) as ID = K é2(VGS - VT )VDS – V ù, where K and VT are the transconductance parameter and the threshold voltage, respectively. Assuming that VDS is constant for both M1 and M2, both the differential-mode and the common-mode transconductance gains can be derived as GDM = GCM = 2KVDS, which can thus be tuned by varying VDS.

The high value of common-mode transconductance is undesirable since it may result in regenerative feedback loops in high-order filters. To improve the CMRR transistor and avoid the formation of such loops, M10 is used to bias the transconductor thus transforming it from a pseudodifferential to a fully differential transconductor [51]. Transistors M11 and M14 constitute a floating voltage source, thus maintaining a constant drain-source voltage for M1 and M2.

The nonlinearities in the voltage to current transfer of this stage are mainly due to three effects. The first is the finite impedance levels at the sources of the cascode devices, which cause a signal-dependent variation of the corresponding drain-source voltages of M1 and M2. A fast-floating voltage source and large cascode transistors therefore need to be used to minimize this nonlinearity. The second cause of nonlinearity is the variation of carrier mobility m of the input devices M1 and M2 with VGS – VT, which becomes more apparent when short-channel devices are used (K = mCoxW/2L). A simple first-order model for transverse-field mobility degradation is given by m = m0/(1 + q(VGS - VT)), where m0 and q are the zero field mobility and the mobility reduction parameter, respectively. Using this model the third-order distortion can be determined by a Maclaurin series expansion as q2/4(1 + q(VCM - VT)) [52]. This expression cannot be regarded as exact, although is useful to obtain insight. Furthermore, it is valid only at low frequencies, where reactive effects can be ignored and the coefficients of the Maclaurin series expansion are frequency independent. At high frequencies or when very low values of distortion are predicted by the Maclaurin series method, a generalized power series method (Volterra series) must be employed [53,54]. Finally, a further cause of nonlinearity is mismatch between M1 and M2 which can be minimized by good layout. A detailed linearity analysis of this transconductance stage is presented in Ref. [55].

To provide a load for the main transconductor cell, a similar cell implemented by p-devices is used. The gates of the linear devices M5 and M6 are now cross coupled with the drains of the cascode devices M7 and M8. In this way, weak positive feedback is introduced. The differential-mode output resistance can now become negative and is tuned by the VDS of M5 and M6 (M12 and M13 form a floating voltage source), while the common-mode output resistance attains a small value.

When connected to the output of the main transconductor cell as shown in Figure 24.33, the cross- coupled p cell forms a high-ohmic load for differential signals and a low-ohmic load for common-mode signals, resulting in a controlled common-mode voltage at the output [52,56]. CMRR can be increased even further using M10 as described previously. Transistor M9 is biased in the triode region of operation and is used to compensate the offset common-mode voltage at the output.

The key performance parameter of an integrator is the phase shift at its unity gain frequency. Deviations from the ideal -90° phase include phase lead owing to finite DC gain and phase lag owing to high- frequency parasitic poles. In the transconductor design of Figure 24.33, DC gain is traded for phase accuracy, thus compensating the phase lag introduced by the parasitic poles. The reduction in DC gain for increased phase accuracy is not a major problem for bandpass filter applications, since phase accuracy at the center frequency is extremely important while DC gain has to be adequate to ensure that attenuation specifications are met at frequencies below the passband.

From simulation results using parameters from a 0.8 mm CMOS process, with the transconductor unity gain frequency set at 50 MHz, third-order intermodulation components were observed at –78 dB with respect to the fundamental signals (two input signals at 49.9 and 50.1 MHz were applied, each at 50 mVpp).

A Gm-C Bandpass Biquad

Filter Implementation

The implementation of on-chip high-Q resonant circuits presents a difficult challenge. Integrated passive inductors have generally poor quality factors which limits the Q of any resonant network in which they are employed. For applications in the hundreds of megahertz to a few gigahertz, one approach is to implement the resonant circuit using low-Q passive on-chip inductors with additional Q-enhancing circuitry. However, for lower frequencies (tens of megahertz), on-chip inductors occupy a huge area and this approach is not attractive.

As disscussed above, an alternative method is to use active circuitry to eliminate the need for inductors. Gm-C based implementations are attractive owing to their high-speed potential and good tuneability. A bandpass biquadratic section based upon the transconductor of Figure 24.33 is shown in Figure 24.34. The transfer function of Figure 24.34 is given by:

Ro represents the total resistance at the nodes owing to the finite output resistance of the transcon- ductors. R represents the effective resistance of the linear region transistors in the transconductor (see Figure 24.33), and is used here to introduce damping and control the Q. From Eq. (24.48) it can be shown that wo » g m /C, Q » g m Ro/( 2 + RoRg m) ,Qmax = Q½R =0 = (g mRo )/2 and Ao = gmQ. Thus, gm is used to set the central frequency, R to control the Q, and gmi to control the bandpass gain Ao. A dummy gmi is used to provide symmetry and thus better stability owing to process variations, temperature, and aging.

One of the main problems when implementing high-Q high-frequency resonators is maintaining stability of the center frequency wo and the quality factor Q. This problem calls for very careful layout

where Vmax is the maximum root mean square (RMS) voltage across the filter capacitors, C the total capacitance, k the Boltzman’s constant, T the absolute temperature, and x the noise factor of the active circuitry (x = 1 corresponds to output noise equal to the thermal noise of a resistor of value R = 1/gm, where gm is the transconductor value used in the filter).

In practice the dynamic range achieved will be less than this maximum value owing to the amplification of both noise and intermodulation components around the resonant frequency. This is a fundamental limitation, and the only solution is to design the transconductors for low noise and high linearity. The linearity performance in narrowband systems is characterized by the spurious-free dynamic range (SFDR). SFDR is defined as the signal to noise ratio (SNR) when the power of the third-order inter- modulation products equals the noise power. As shown in [55], the SFDR of the resonator in Figure 24.34 is given by

where IM3,int is the third-order intermodulation point of the integrator used to implement the resonator. The SFDR of the resonator thus deteriorates by 6 dB if the quality factor is doubled, assuming that the output swing remains the same. In contrast, implementing a resonant circuit using low-Q passive on- chip inductors with additional Q-enhancing circuitry leads to a dynamic range amplified by a factor Qo, where Qo is the quality factor of the on-chip inductor itself [57]. However, as stated above, for frequencies in the tens of megahertz, on-chip inductors occupy a huge area and thus the Qo improvement in dynamic range is not high enough to justify the area increase.

Simulation Results

To confirm operation, the filter shown in Figure 24.34 has been simulated in HSPICE using process parameters from a commercial 0.8 mm CMOS process. Figure 24.35 shows the simulated frequency and phase response of the filter for a center frequency of 50 MHz and a quality factor of 50. Figure 24.36

shows the simulated output of the filter when the input consists of two tones at 49.9 and 50.1 MHz, respectively, each at 40 mVpp. At this level of input signal, the third-order intermodulation components were found to be at the same level as the noise. Thus, the predicted SFDR is about 34 dB with Q = 50. Table 24.5 summarizes the simulation results.