Communication-Based Design for Nanoscale SoCs:Advantages of NoC Architectures

Introduction

Systems-on-chip (SoCs) designed at nanoscale domain will soon contain billions of transistors [1]. This makes it possible to integrate large amounts of embedded memory and hundreds of IP cores running multiple concur- rent processes on a single chip. This chapter focuses on the communication-centric SoC design, while the computational aspects are discussed in Chapter 17 [2]. The design of complex SoCs faces a number of design challenges. First, the richness of computational resources places tremendous demands on the communication resources and, consequently, the entire design methodology changes from computation-based design to communication-based design. Second, global interconnects cause severe on-chip synchronization errors, unpre- dictable delays, and high power consumption. Finally, increasing complexity, costs, and tight time-to-market constraints require new design methodologies that favor design reuse at all levels of abstraction [3–5]. As a result, novel on-chip communication architectures that can effectively address all these problems are highly needed.

Owing to their limited bandwidth, legacy bus-based architectures fail to solve the above-mentioned problems. Moreover, a global bus with large capacitive load causes long delays and high-power consumption. While point-to-point communication architectures may provide the required performance, the

design area and lack of scalability become two major issues for implementing complex applications; this is mainly due to the dedicated channels between all the communicating IP pairs [6]. In contrast to these traditional methods, the recently proposed networks-on-chip (NoC) architecture provides a large bandwidth with moderate area overhead [5–9].

Advantages of NoC Architectures

NoC architectures consist of a number of heterogeneous cores such as CPU or DSP modules, video processors, embedded memory blocks, and application-specific components, as shown in Figure 16.1. Each core has an embedded router which connects the core to other nodes in the network via an interconnection network. The advantages of NoCs include scalability, reusability, and predictability as detailed below.

• Scalability. Since the communication between different nodes is achieved by routing packets instead of wires, a large number of cores can be connected without using long global wires. Moreover, as the number of cores in the design increases, the network bandwidth increases accordingly. As a result, the NoC paradigm provides a highly scalable communication architecture.

• Design reuse. The modularity of the NoC approach offers a great potential for reusing the network routers and other IP cores. The routers, interconnect, and lower-level communication protocols can be designed, optimized, and verified only once and reused subsequently in a large number of products. Likewise, the IP cores complying with the network interface can be reused across many different applications.

• Predictability. The structured nature of the global wires facilitates well-controlled and optimized electrical parameters. In turn, these controlled parameters make possible the use of aggressive signaling circuits which can reduce the power dissipation and propagation delay significantly [5].

NoC Design Space

From a design methodology standpoint, designing on-chip networks differs significantly from designing large-scale interconnection networks [10], mainly due to the distinctive cost functions and constraints imposed by the on-chip functionality. For example, the energy consumption is one of the major con- straints in NoC design, while it is hardly a consideration for large-scale networks. Moreover, unlike large- scale networks, NoCs are highly application-specific. Therefore, an ample portion of the design effort will likely go into optimizing the network for a specific application or class of applications.

NoC design problems can be conceived as representing a three dimensional (3D) design space [11]. The first dimension of this space is represented by the communication infrastructure (e.g., network topology and width of the channel links). This dimension defines how nodes are interconnected to each other and reflects the fundamental properties of the underlying network. The second dimension, namely the communication

paradigm, captures the dynamics of transferring messages (e.g., XY versus adaptive routing) inside the network. Finally, the third dimension, application mapping, defines how different tasks that implement the target application are mapped to the network nodes (e.g., how various traffic sources and sinks are distributed across the network). In the design-automation community, design space exploration along each dimension has been considered to some extent without explicitly referring to such a classification.

The simplicity of regular grid architectures, as opposed to the complexity of the fully customized topologies, favors the design approaches where a modular network topology is chosen a priori. Once the topology is fixed, the main design problem becomes mapping the target application to the given topology, while optimizing one or more design variables, such as performance or energy [12–14]. As shown in Figure 16.2, fixing the topology and routing function a priori, requires the least design effort but, at the same time, limits severely the quality of the design one can achieve. The design quality can be improved by evaluating a set of standard topologies (e.g., torus or other higher dimensional meshes) and choosing the best alternative for a particular application; this is because the selection of the network topology has a considerable impact on area, performance, and system power consumption [15,16]. It is also possible to partially customize the network architecture to match the target application. For example, one can optimize the buffer allocation to the network nodes, rather than simply using the uniform buffer allocation [17]. Indeed, the total buffer budget affects the routers area significantly, while its distribution over the routers has a huge impact on performance.

The standard network topologies (e.g., star, tree, torus, hypercube, etc.) are suited for scenarios where we have limited or no knowledge about the traffic in the network. However, when the performance, area, and power that can be harvested by the standard topologies do not satisfy the design constraints, the information about the application-specific communication requirements can be exploited for optimiza- tion purposes [18–20]. By synthesizing fully customized topologies, a much larger portion of the design space can be explored compared to simply limiting the design to standard topologies.

Obviously, the actual level of customization, illustrated in Figure 16.2, will be determined by factors such as design cost, product volume, and market conditions. Nevertheless, effective design automation tools targeting different customization levels, similar to those discussed in the following sections, should be available to designers to address a wide range of design problems.

In the remaining part of this chapter we first overview the engineering aspects of NoC design. Toward this end, concrete results ranging from algorithms for application mapping [12–14], all the way down to silicon implementation [21–23] will illustrate the NoC paradigm in action. As the network paradigm moves

Design effort

Fixed standard architecture

Customized standard infrastructure

Customized infrastructure

• Fixed topology

• Buffer allocation

• Arbitrary topologies

• Explore mapping and routing

• Fixed topology and routing

• Explore mapping

• A set of standard topologies

• Explore mapping and routing

Increased customization level and flexibility

Design quality

closer to silicon, designing NoCs becomes increasingly based on concrete metrics for energy and performance. Consequently, the NoC design becomes more of a science on its own. Consequently, the science of NoC design is overviewed in Section 16.3, while its interplay with the engineering aspects is discussed in Section 16.4.

Engineering Issues in NoC Design

The engineering aspects of NoC design are mostly related to practical issues ranging from clocking and signaling strategies at physical level, all the way up to operating system design at software level [7]. Finding solutions to problems into this category is very important for bringing the NoC paradigm closer to practice. A typical example of work dealing primarily with the engineering aspects of NoC design is the aSoC communication architecture, which provides one of the first examples of an NoC implementation [21]. Similarly, the SPIN interconnect architecture implements a 32-port network architecture supporting best-effort traffic in a 0.13 mm process [22]. A more recent implementation considers a highly optimized hierarchical star topology [23]. Bertozzi et al. [24] present a design flow starting from a high-level application specification that incorporates topology mapping and selection to derive an optimized NoC configuration with respect to different design objectives.

Some applications require guarantees on packets delivery time. Generating NoC architectures with guaranteed services have been investigated [25–27]. In Refs. [25,26], the Quality of Service (QoS) is ensured by allocating the necessary bandwidth under a time division multiplexing scheme and using routers which support both guaranteed and best-effort services. In [27], the authors an asynchronous NoC with wormhole routing and provide service guarantees through the use of virtual channels. Finally, the approach in Ref. [28] provides QoS based on different traffic classes.

Efficient estimation and optimization of power consumption is also an important problem in NoC design. Wang et al. [29] present a power model for routers and a power-performance simulator for interconnection networks. Ye et al. [30] analyze the power consumption in switch fabrics and propose a system-level energy model for NoCs. Finally, a power-performance evaluator for mesh-based NoCs is presented in Ref. [31].