CMOS/BiCMOS Technology:Recent Process Issues and Summary of CMOS/BiCMOS Technology.

By -
Recent Process Issues

According to the International Technology Roadmap for Semiconductors [131], gate length, Lg, of MOSFET would be shrunk to sub-15 nm toward 2013. Sub-50 nm Lg device [132–134] or even sub-15 nm device [135] already are reported. These ultra-small geometry devices have several process issues as shown in Figure 2.27. In this section, process issues for realizing future downsized CMOS devices are introduced.

High Dielectric Constant, κ, Film for Gate Insulator

Since ultra-small geometry device requires ultra-thin gate insulator thickness of less than 3 nm, direct tunneling current through gate oxide is observed. In some cases, this tunnel current might be accepted to realize high driving capability [136–140]. Also, SiON gate insulator with sufficient nitridation can reduce

CMOS-BiCMOS Technology-0033

gate leakage current significantly [141,142]. However, in taking account of power consumption of standby mode, especially for mobile applications, these tunneling currents become a severe problem. Because of high dielectric constant, high-κ material of even relatively thick thickness can realize ultra-thin equivalent oxide thickness (EOT) so it can reduce tunneling currents through the gate insulator [143].

Various high-κ films are widely studied as shown in Table 2.3. Although Al2O3 [144] and Ta2O5 [35,36] were widely noticed in the early stage of high-κ material research, Hf-based material, such as HfO2 [156, 157] or HfSiON [158,159], have become promising films for sub-50 nm gate length FETs, because of realizing thermal stability and high effective mobility.

For manufacturing high-κ gate insulator CMOS FETs, there are still reliability problems, such as degradation mechanisms [160–163]. Moreover, dielectric constants of gate dielectrics and sidewalls may be very different from each other, resulting in a large discontinuity in dielectric constant; therefore, electric field distribution affected by gate-edge structure should be investigated [164]. In taking account of applying for analog applications, low-frequency behavior is also important [165,166].

For ultra-small geometry FETs with ultra-thin EOT by high-κ gate insulator, metal gate electrode devices are demonstrated to prevent gate electrode resistance problem [167]. Also, these devices can avoid both gate depletion and boron penetration problems. Promising materials as metal gate electrode are TiN [168–170] and TaN [171,172], and dual metal gate structure by using TiN (for p-MOS) and TaSiN (for n-MOS) is also reported [173].

Shallow Junction for Source and Drain and Extensions

Since ultra-small geometry device requires ultra-shallow source–drain diffused layers, especially exten- sions which locate beneath sidewall, to prevent short-channel effect, Halo implantation technique [174–178] is introduced. By using tilted implantation, counter-doping is carried out around extensions to realize abrupt profiles of extensions as shown in Figure 2.28. Optimizations of annealing process [179] and doping process [180] are also important. Halo extensions sometimes cause large junction capacitance and junction leakage. Tilted nitrogen implantation is a useful technique for avoiding these problems [181, 182].

Generally, salicide technique is adopted on shallow source–drain diffused layers to reduce parasitic resistance. Co salicide process is widely used for ultra-small devices; however, this process sometimes causes the problem of junction leakage. Optimization of trade-off relationship between junction leakage and parasitic resistance is also important [183,184].

Recently, for avoiding junction leakage problem, elevated source–drain structures are demonstrated by using selective epitaxial technique [185–187] as shown in Figure 2.29. Alternative techniques, for example, solid-phase epitaxial method [188] and laser thermal annealing process [189] are also demonstrated.

Mobility Enhancement Technique

Ultra-small geometry device requires low-κ films as gate insulator to reduce gate leakage current; however, interstitial state between low-κ film and silicon causes reduction of mobility [190]. Strained layer by SiGe

CMOS-BiCMOS Technology-0034

film can enhance the carrier mobility [191–196] as shown in Figure 2.30. These effects are observed even in ultra-small geometry devices, such as 45 nm gate length FET [197] and 40 nm gate length FET [198]. In contrast, as well known, carrier mobility depends on orientation of silicon wafer. In fact, p-MOSFET realizes high performance on (110) wafer and n-MOSFET on (100) wafer. By using these characteristics,  hybrid substrate structures are demonstrated [199–201].

Modeling Issue

As the de facto industry standard MOS model, BSIM has been widely used [202]. Latest version BISIM4 can be applied for high-frequency analog circuits [203] or recent process issues [204].

In the case of modeling ultra-small geometry devices, it is necessary to take account of quantum-level phenomena [205] or ballistic effects [206], as a result, physics-based simulation [207] and Monte Carlo simulation [208] are demonstrated. However, pragmatic compact model is important to simulate large- scale level. PSP MOS model [209,210] and HiSIM [211] are useful compact models in the future LSI applications.

Summary

We described CMOS and BiCMOS technology in this section. CMOS is the most important device structure for realizing the future higher-performance devices required for multimedia and other demand- ing applications. However, certain problems are preventing the downsizing of device dimensions. To prevent these problems, three-dimensional structures, such as vertical MOSFET [212], FIN-type structure [213,214], and double-gate structure [215] are introduced. In taking account of manufacturing, planer structure is still important [216]. Sub-10 nm CMOS devices have been already reported [217].

BiCMOS technology is also important, especially for mixed-signal applications. However, CMOS device performance has already been demonstrated for RF applications, and thus analog CMOS circuit technology will be very important for realizing the production of analog CMOS.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more