CMOS Fabrication:CMOS Unit Processes and Wafer Manufacture

CMOS Unit Processes

In this section we introduce each of the major processes required to fabricate CMOS ICs. First, however, we will discuss wafer preparation, even though it is not a unit process, because it is important to know how manufacturers produce wafers. After that, we will present the unit processes that fabrication facilities use to produce ICs. Grouped by function, they are thermal oxidation, doping processes, photolithography, thin-ﬁlm removal, and thin-ﬁlm deposition.

Wafer Manufacture

Silicon is the second-most abundant element in the Earth’s crust; however, it occurs exclusively in compounds. Elemental silicon is a man-made material reﬁned from these various compounds, the most common being silica (impure SiO2). Modern ICs must be fabricated on ultrapure, defect-free slices of single-crystalline silicon, called wafers.

Metallurgical-Grade Silicon (MGS)

Wafer production requires three general processes: silicon reﬁnement, crystal growth, and wafer formation. Silicon reﬁnement begins with the reduction of silica in an arc furnace at roughly 2000°C with a carbon source. The carbon effectively “pulls” the oxygen from the SiO2 molecules, thus chemically reducing the oxide into roughly 98% pure silicon, referred to as MGS. The overall reduction is governed by the following equation:

Electrical-Grade Silicon (EGS)

MGS is not pure enough for microelectronic device applications because the electronic properties of a semiconductor such as silicon are extremely sensitive to impurity concentrations. Impurity levels measured at parts per million or less can have dramatic effects on carrier mobilities, lifetimes, etc. It is therefore necessary to further purify the MGS into what is known as EGS. EGS is produced by chlorinating grounded MGS as shown in the following representative, unbalanced equation:

Since the reaction by-products are liquids at room temperature, ultrapure EGS can be obtained from fractional distillation and chemical reduction processes. The resultant EGS is in the form of polycrystalline chunks.

Czochralski (CZ) Growth

To achieve a single-crystalline form, the EGS must be subjected to a process called CZ growth. A schematic representation of the CZ growth process is shown in Figure 12.1. The polycrystalline EGS is melted in a large quartz crucible. A small seed crystal of known orientation is introduced into the surface of the silicon melt. The seed crystal, rotating in one direction, is slowly pulled from the silicon melt, which is rotating in the opposite direction. Solidiﬁcation of the silicon onto the seed results in the formation of a growing crystal (called a boule or ingot) that assumes the crystallo- graphic orientation of the seed. In general, the slower the pull rate (typically measured in millimeter per hour), the larger the diameter of the silicon crystal. The silicon boule is then turned down to the appropriate diameter, and ﬂats or notches are ground into the surface of the boule to indicate a precise crystal orientation. Using a special saw, the silicon boule is cut into thin wafers. The wafers are ﬁnished by using a chemical-mechanical polishing (CMP) process, as discussed in Section 12.1.5,

to yield a mirror-like ﬁnish on one side of the wafer. Although devices are fabricated entirely within the top 2 µm of the wafer, for adequate mechanical support, the ﬁnal wafer may be of the order of 1 mm thick (thickness increases with wafer diameter).

Thermal Oxidation

Silicon, when exposed to an oxidant at elevated temperatures, will readily form a thin layer of oxide on all exposed surfaces. Silicon’s native oxide is in the form of silicon dioxide (SiO2). With respect to CMOS fabrication, SiO2 can serve as a high-quality dielectric in device structures such as gate oxides. During processing, thermally grown oxides can be used as implantation, diffusion, and etch masks. The dominance of silicon as a microelectronic material can be attributed to the existence of this high-quality native oxide and the resultant near-ideal silicon–oxide interface.

Figure 12.2 depicts the basic thermal oxidation process. The silicon wafer is exposed at high temper- atures (typically, 900–1200°C) to a gaseous oxidant such as molecular oxygen (O2) and water vapor (H2O). For obvious reasons, oxidation in O2 is called dry oxidation, whereas in H2O it is called wet oxidation. The gas–solid interface forms a stagnant layer through which the oxidant must diffuse to reach the surface of the wafer. Once at the surface, the oxidant must again diffuse through the oxide layer present. As the oxidant species reaches the silicon–oxide interface, one of the following two reactions occurs:

FIGURE 12.2 Simple model for thermal oxidation of silicon. Notice the oxidant concentrations (boundary condi- tions) in the gas, oxide, and silicon.

It should be emphasized that reactions speciﬁed by Eq. (12.3) and Eq. (12.4) occur at the silicon–oxide interface, where silicon is consumed in the reaction. As seen in Figure 12.2, the position of the original interface is at ~50% of the thickness of the oxide.

The rate of thermal oxidation is a function of temperature and rate constants. The rate is directly proportional to temperature. The rate constants are, in turn, a function of gas partial pressures, oxidant type, and silicon wafer characteristics such as doping type, doping concentration, and crystallographic orientation. In general, dry oxidation yields a denser and thus higher quality oxide than does wet oxidation. However, wet oxidation occurs at a much higher rate compared to dry oxidation. Depending on the temperature and existing thickness of oxide present, the overall oxidation rate can be either diffusion limited (e.g., thick oxides at high temperatures) or reaction-rate limited (e.g., thin oxides at low temperatures). Practically speaking, oxide thicknesses are limited to less than a few thousand angstroms and to <1 µm for dry and wet oxidation, respectively.

In a modern fabrication facility, oxidation occurs in either a tube furnace or in a rapid thermal-processing (RTP) tool, as shown schematically in Figure 12.3. A tube furnace consists of a quartz tube surrounded by heating element coils. The wafers are loaded into the heated tube, where oxidants can be introduced through inlets. The function of the RTP is similar, except that the thermal source is heating lamps.

Doping Processes

Controlled introduction of dopant impurities into silicon is necessary to affect majority carrier type, carrier concentration, carrier mobility, carrier lifetime, and internal electric ﬁelds. Common n-type dopants in Si are P, As, and Sb. The common p-type dopant in Si is B. The two primary methods of dopant introduction are solid-state diffusion and ion implantation. Historically, solid-state diffusion has been an important doping process; however, ion implantation is the preferred method in modern CMOS fabrication.

Ion Implantation

The workhorse method of introducing dopants into the near-surface region of wafers is a process called ion implantation. In ion implantation, dopant atoms (or molecules) are ionized, then accelerated through a large

electric potential (a few kilovolts to megavolts) toward a wafer. The highly energetic ions bombard and thus implant into its surface. Obviously, this process leads to a high degree of lattice damage, which is generally repaired by annealing at high temperatures. Because the ions do not necessarily come to rest at a lattice site, an anneal is required to electrically activate the dopant impurities by thermally agitating them into lattice sites. Figure 12.4 shows a schematic diagram of an ion implanter. The ions are generated by an RF ﬁeld in the ion source, from which they are subsequently extracted to a mass spectrometer. The spectrometer allows only ions with a user-selected mass to enter the accelerator, where the ions are passed through a large potential ﬁeld. The ions are then scanned via an electrostatic lens across the surface of the wafer.

A ﬁrst-order model for an implant doping proﬁle is given by a Gaussian distribution described mathematically as

where Np is the peak concentration, Rp the projected range, and ∆Rp the straggle. By inspection, Rp should be identiﬁed as the mean distance the ions travel into the silicon and ∆Rp as the associated standard deviation. Figure 12.5 illustrates a typical ion implant proﬁle. Obviously, Np occurs at a depth of Rp. Moreover, the area under the implant curve corresponds to what is referred to as the implant dose Qimp, given mathematically as

Localized implantation is achieved by masking-off regions of the wafer with an appropriately thick material such as oxide, silicon nitride, polysilicon, or photoresist. Since implantation will occur in the masking layer, the thickness must be of sufﬁcient magnitude to stop the ions before they reach the silicon

into a mass spectrometer. Once successfully through the spectrometer, the ions are accelerated to the desired magnitude. An electrostatic lens scans the ion beam on the surface of a wafer to achieve the appropriate dose. Electrostatically, the ions can be counted where an integrator can provide the real-time dose.

substrate. Compared with solid-state diffusion, ion implantation has the advantages of being a low- temperature and a highly controlled process.

Solid-State Diffusion

Solid-state diffusion is a method of introducing and redistributing dopants. In this section, we will study solid-state diffusion primarily to gain insight into “parasitic” dopant redistribution during thermal processes. In typical CMOS process ﬂows, dopants are introduced via ion implantation into localized regions, which are subsequently processed at high temperatures. Solid-state diffusion inher- ently occurs in these high-temperature steps, thus spreading out the implant proﬁle in three dimen- sions. The net effect is to shift the boundary of the implant from its original implant-deﬁned position,

both laterally and vertically. This thermal smearing of the implant proﬁles must be accounted for during CMOS process ﬂow development. If not, the ﬁnal device characteristics can differ signiﬁcantly from those expected.

Solid-state diffusion (or simply diffusion) requires two conditions: a dopant concentration gradient and thermal energy. Diffusion is directly proportional to both. An implanted proﬁle (approximated by a delta function at the surface of the wafer) diffuses to ﬁrst-order as

where Qimp is the implant dose, D the diffusivity of the dopant, and t the diffusion time. Figure 12.6 illustrates this so-called limited-source diffusion of a one-dimensional implant proﬁle. Notice that the areas under the respective curves for a given time are equal.

Photolithography

In the fabrication of CMOS it is necessary to localize processing effects to form a multitude of features simultaneously on the surface of the wafer. The collection of processes that accomplishes this important task—using ultraviolet light, a photomask, and a light-sensitive chemical resistant polymer—is called photolithography. Although many different categories of photolithography exist, they all share the same basic processing steps resulting in micron-to-submicron features generated in the light-sensitive polymer called photoresist. The photoresist patterns can then serve as ion implantation masks and etch masks during subsequent processing steps.

Figure 12.7 outlines the major steps required to implement photolithography patterning of a thermally grown oxide. Photoresist, a viscous liquid polymer, is applied to the top surface of the oxidized wafer. The application typically occurs by dropping (or spraying) a small volume of photoresist onto a rapidly rotating wafer, yielding a uniformly thin ﬁlm on the surface. Following spinning, the coated wafer is softbaked on a hot plate, which drives out most solvents from the photoresist and improves adhesion to the underlying substrate. Next, the wafers are exposed to ultraviolet light through a mask (or reticle) that contains the layout patterns for a given drawn layer. The three general methods used to expose photoresist are contact, proximity, and projection photolithography.

In both contact and proximity photolithography, the mask and the wafers are in contact and in close proximity, respectively, to the surface of the photoresist. Here the mask features are of the same scale as the features to be exposed on the surface. In projection photolithography, which is the dominant type of patterning technology, the mask features are drawn at a larger scale (e.g., 5× or 10×) relative to the features exposed on the surface. This is accomplished with a projection stepper that uses reduction optics to project an image of the mask onto the photoresist surface. For positive-tone photoresist, the ultraviolet light breaks molecular bonds, making the exposed regions more soluble. For negative-tone photoresist, exposure causes polymerization and thus less solubility. The exposed resist-coated wafer is developed in an alkaline solution. Whether a positive image or negative image relative to the mask patterns is generated depends on the formulation of the photoresist. To harden the photoresist for improved etch resistance and to improve adhesion, the newly developed wafers often are hardbaked. At this point, the wafer can be etched to transfer the photoresist pattern into the underlying thin ﬁlm. Etch processes will be discussed in the next section.

Resolution

In general, a given projection stepper has three critical parameters: resolution, depth of focus (DOF), and pattern registration. The diffraction of light caused by the various interfaces in its path limits the minimum printable feature size (Figure 12.8). Resolution is deﬁned as the minimum feature size, M, that can be printed on the surface of the wafer given by

where n is the index of refraction of the space between the wafer and the lens and θ the acute angle between the focal point on the surface of the wafer and the edge of the lens radius. Notice that M is directly proportional to wavelength, hence diffraction effects are the primary limitation in printable feature size. To a limit, the NA of the projection lens can be increased to help combat diffraction effects because large NA optics have an increased ability to capture diffracted light.

DOF

DOF of the projection optics limits the ability to pattern features at different heights. Mathematically, DOF is given by

(a) no registration error; (b) x–y registration error; (c) z-rotation registration error; (d) x–y and z-rotation error. Other registration errors exist, but are not discussed here.

where c2 is a constant ranging in value from 0.5 to 1. As is apparent from Eq. (12.8) and Eq. (12.10), a fundamental trade-off exists between minimum feature size and DOF. In other words, to print the smallest possible features, the surface topography must be minimized (often achieved through the use of CMP as discussed in the next section).

Aligning Masks

During CMOS fabrication numerous mask levels (e.g., active, poly, and contacts) are printed on the wafer. Each of these levels must be accurately aligned to one another. Registration is a measure of the level-to- level alignment error. Registration errors occur in x-, y-, and z-rotations, as illustrated in Figure 12.10.

Emerging Lithographic Technologies

At ﬁrst glance, it would seem that the minimum feature size could not be less than the wavelength of the light. However, advanced techniques such as optical proximity correction (OPC) and wavefront engineering of photomasks have been developed to push the resolution limits below the exposure wavelength.

There is signiﬁcant effort to develop lithographic techniques that can pattern features with dimensions measured in the nanometer regimen. Most of these methods employ the use of small-wavelength light sources in the extreme ultraviolet to x-ray wavelengths. Extreme ultraviolet (EUV) lithography is one of the leading candidates for producing features below 50 nm.

Thin-Film Removal

After photolithography, usually one of the two processes is performed: thin-ﬁlm etching, which is used to transfer the photoresist patterns to the underlying thin ﬁlm(s) and ion implantation, which employs the photoresist patterns to block the dopants from selected regions of the wafer surface. Here, we discuss thin- ﬁlm etching processes based on wet chemical etching and dry-etching techniques. We also discuss the CMP process that is used to remove unpatterned thin ﬁlms.

Thin-Film Etching

After a photoresist pattern is generated, either wet or dry etching is commonly used to transfer patterns into underlying ﬁlms. Etch rate (thickness removed per unit time), selectivity, and degree of anisotropy are key parameters for both wet and dry etching. Etch rates are typically a strong function of solution (or gas) concentrations and temperature. Selectivity, S is deﬁned as the etch rate ratio of one material to another, given by the selectivity equation

where Rl is the lateral etch rate and Rv the vertical etch rate. If Af = 1, the etchant is completely anisotropic. However, if Af = 0, the etchant is completely isotropic. In photolithography, the degree of anisotropy is a major factor in the achievable resolution. Figure 12.11 illustrates the effects of etch bias (i.e., dﬁlm - dmask) on the ﬁnal feature size. For the submicron features that are required in CMOS, dry-etch techniques are preferred over wet-etch processes because they generally have a higher degree of anisotropy. Both wet and dry etching methods are applied to the removal of metals, semiconductors, and insulators.

Wet Etching

In wet etching, a chemical solution is used to remove material. In CMOS fabrication, wet processes are used for cleaning wafers and for thin-ﬁlm removal. Wet-cleaning processes are repeated numerous times throughout a process ﬂow. Some are targeted toward removal of particulate; others are intended to remove organic and inorganic surface contaminants. Wet etchants can be isotropic (i.e., etch rate is the same in all directions), or anisotropic (i.e., etch rate differs in different directions). However, most of the wet etchants used in CMOS fabrication are isotropic. Wet etchants generally tend to be highly selective compared with the dry-etch processes. To improve the etch uniformity and to aid in the removal of particulate, it is common to ultrasonically vibrate the etchant and use microcontrollers to accurately control the temperature of the bath. Once an etch is completed, the wafers are rinsed in deionized water and then spun dry.

Dry Etching

The three general categories of dry-etch techniques in CMOS fabrication are sputter etching, plasma etching, and reactive-ion etching (RIE). Figure 12.12 schematically illustrates a sputter etch process. An inert gas (e.g., argon) is ionized, where the ions are accelerated through an electric ﬁeld established between two conductive electrodes, called the anode and the cathode. A vacuum in the range of milliTorr must exist between the plates to allow the appropriate ionization and transfer of ions. Under these conditions, a glow discharge or plasma is formed between the electrodes. The plasma consists of positively charged ions and electrons that respond in opposition to the electric ﬁeld. The wafer that is placed on the cathode is bombarded by positively charged ions that cause material to be ejected off the surface. Essentially, sputter etching is atomic-scale sandblasting. A DC power supply can be used for sputter etching of conductive substrates, while an RF supply is required through capacitive coupling to etch nonconductive substrates. Sputter etching does not tend to be selective, but is very anisotropic.

A simpliﬁed diagram of a plasma etch system is shown in Figure 12.13. A gas or a mixture of gases (e.g., halogens) is ionized, producing reactive species called radicals. A glow discharge or plasma is formed between the electrodes. The radicals chemically react with the surface material, where the reaction products are in the gas phase and are pumped away through a vacuum system. Plasma etching can be very selective, but is typically highly isotropic.

While sputter etching is a purely mechanical process and plasma etching a purely chemical one, RIE is a combination of sputter etching and plasma etching as shown schematically in Figure 12.14. In RIE, a gas or mixture of gases (e.g., ﬂuorocarbons) is ionized, generating radicals and ionized species, both of which interact with the surface of the wafer. In CMOS fabrication, RIE is the dominant etch process because it can provide the beneﬁts of both sputter etching and plasma etching: it can be highly selective and highly anisotropic.

CMP

Figure 12.15 depicts the key features of CMP. In CMP, an abrasive chemical solution, called a slurry, is introduced between a polishing pad and the wafer. Material on the surface of the wafer is removed by both a mechanical polishing component and a chemical reaction component. In modern CMOS fabrication, CMP is a critical process that planarizes the surface of the wafer prior to photolithography. The planar surface allows the printed feature size to be decreased. CMP can remove metals, semiconductors, and insulators.

Thin-Film Deposition

CMOS ICs require insulators, conductors, and semiconductors. Examples of the latter include crystalline silicon for active areas and polycrystalline silicon for gate electrodes or local area interconnects. Gate dielectrics, device isolation, metal-to-substrate isolation, metal-to-metal isolation, passivation, etch masks, implantation masks, diffusion barriers, and sidewall spacers may use insulators such as Si3N4, SiO2, or doped glasses. Conductors—such as aluminum, copper, cobalt, titanium, tungsten, and titanium nitride—are employed for local interconnects, contacts, vias, diffusion barriers, global interconnects, and bond pads.

In this section, we discuss methods of depositing thin ﬁlms of insulators, conductors, and semicon- ductors. The two primary categories of thin-ﬁlm deposition are physical vapor deposition (PVD) and chemical vapor deposition (CVD). Electrodeposition, used to deposit copper for back-end interconnects, is less common and will be brieﬂy introduced.

Deposited ﬁlms may be characterized by several factors. Of prime importance are inherent ﬁlm quality as it relates to compositional control, low contamination levels, low defect density, and predictable and stable electrical and mechanical properties. Moreover, ﬁlm thickness uniformity must be understood and controlled to high levels. To achieve highly uniform CMOS parameters across a wafer, it is common to have to control the ﬁlm thickness uniformity to <±5 nm across the surface of the wafer. In addition, ﬁlm uniformity over topographical features—called step coverage—is of critical importance. As depicted in Figure 12.16, good step coverage results in uniform thickness over all surfaces. In contrast, poor step coverage results in signiﬁcantly less thickness on vertical surfaces relative to surfaces parallel to the surface of the wafer.

Related to step coverage is what is referred to as “gap ﬁll”. This applies to depositing material into a high-aspect ratio opening such as contacts or gaps between adjacent metal lines. Figure 12.17 illustrates a deposition with good gap ﬁll and a deposition that yields a poor one (also called a “keyhole” or void).

PVD

In PVD, physical processes produce the constituent atoms (or molecules) that pass through a low-pressure gas phase and subsequently condense on the surface of the substrate. Common PVD processes are evaporation and sputter deposition. Either can be used to deposit a wide range of insulating, conductive, and semi- conductive materials. However, one drawback of PVD is that the resultant ﬁlms often have poor step coverage.

Evaporation is one of the oldest methods of depositing thin ﬁlms of metals, insulators, and semicon- ductors. The basic process of evaporation is shown in Figure 12.18. The material to be deposited is heated beyond its melting point in a high vacuum chamber, where the vapor form of the material coats all surfaces exposed within the mean free path of the evaporant. The heat source can be either a heating ﬁlament or a focused electron beam.

In simple terms, sputter deposition is similar to sputter etching as discussed in Section 12.1.5, except that the wafer serves as the anode and the cathode is a target material to be deposited. Figure 12.19 outlines a simpliﬁed sputter deposition process. An inert gas such as argon is ionized in a low-

pressure ambient, where the positively charged ions are accelerated through the electric ﬁeld toward the target––an ultrahigh-purity disk of material to be deposited. The bombardment of the target with the ions sputters (or ejects) target atoms (or molecules), resulting in their transit to the wafer surface to form a thin ﬁlm. Sputter deposition, similar to sputter etching, requires a DC supply for conductors; however, a capacitively coupled RF supply must be used to deposit nonconductive materials.

CVD

In CVD, reactant gases are introduced into a chamber where chemical reactions between the gases at the surface of the substrate produce a desired ﬁlm. Common CVD processes are atmospheric pressure (APCVD), low-pressure (LPCVD), and plasma-enhanced (PECVD). Again, a wide variety of insulators, conductors, and semiconductors can be deposited by CVD. Most importantly, the resultant ﬁlms tend to have better step coverage than those deposited by PVD processes. APCVD occurs at relatively low temperatures in an apparatus similar to an oxidation tube furnace, where an appropriate reactive gas is passed over the wafers (see Figure 12.3). As depicted in Figure 12.20, LPCVD occurs in a reactor in the pressure range of milliTorr to a few Torr. Compared to APCVD, the low-pressure process can yield highly conformal ﬁlms, but at the expense of a higher deposition temperature. Figure 12.21 shows a

schematic diagram of a PECVD reactor. In PECVD, a plasma is used to impart energy for the surface reactions, hence allowing for lower temperature deposition. In comparison, PECVD has the advantage of being a low-temperature and a highly conformal process. It should be noted that during epitaxial growth of crystalline semiconductors (e.g., Si or Si1−xGex) graded layers are often deposited using a CVD process.

Electroplating

In modern copper (Cu) backends, electroplating is used to deposit a conformal ﬁlm of Cu on the conductive regions of the substrate. Electroplating is a method where the wafer is immersed in a bath of an electrolyte (often a salt solution) and an electrical current is driven through the solution from an electrode to the wafer (also serving as an electrode). This process causes a reaction to occur precipitates the metal (e.g., Cu) out of the electrolyte to the surface of the substrate.

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