CMOS Fabrication:CMOS Process Integration.

CMOS Process Integration

Process integration is the task of combining a deliberate sequence of unit processes to fabricate integrated microelectronic devices such as PMOS transistors, NMOS transistors, resistors, capacitors, and diodes. A typical CMOS technology consists of a complex arrangement of unit processes in which several hundred steps are required to manufacture ICs on a silicon wafer. Groups of unit processes are combined to form integration modules. For example, the gate module would include a speciﬁc sequence of unit processes that would yield a gate electrode on a thin, gate dielectric. The modules can then be combined to yield the overall process ﬂow (or process sequence). The process ﬂow can be divided into front-end-of-the- line (FEOL) and back-end-of-the-line (BEOL) processes. A typical process ﬂow, consisting of numerous modules, is shown in block diagram form in Figure 12.22.

FEOL

Generally, FEOL refers to all processes preceding salicidation and includes all processes required to fully form isolated CMOS transistors. Figure 12.22 shows the FEOL beginning with the selection of the starting

material (i.e., type of silicon wafer to be used). Then the shallow-trench isolation (STI) module forms regions of dielectric between regions of active area. Next, the wells (or tubs) are formed, followed by the gate module, which includes all processes to properly deﬁne gate electrodes on a thin oxide. The FEOL concludes with the source/drain module. Its processes form low-doped drain (LDD) extensions and the source/drain regions themselves.

Major differences in the design of the FEOL are often due to the speciﬁc technology requirements. For instance, high-speed logic is often implemented with the selection of silicon-on-insulator (SOI) wafers or an SiGe channel structure. The SOI process generally yields devices with lower capacitance than does a comparable bulk technology. Whereas, SiGe technologies are fabricated using an epitaxtial growth of a strained channel that yield higher electron (and hole) mobilities. Regardless of the speciﬁc type of FEOL technology, the overall process ﬂow is similar in most cases.

BEOL

All processes subsequent to source/drain formation fall within the BEOL. Hence, BEOL processes “wire” transistors together using multiple layers of dielectrics and metals. The BEOL begins with the salicidation of the polysilicon and source/drain regions. The remaining BEOL processes proceed in repetitive sets of modules to yield lateral and vertical interconnects isolated from one another with dielectrics. Conven- tionally, aluminum (Al) metallization and tungsten (W) contact and via plugs are used in the BEOL. Higher performance (i.e., lower resistance and lower capacitance) BEOL are implemented using a Cu dual-Damascene/low-k dielectrics for the respective conducting and insulating materials.

It is important to understand that there is a high degree of interrelationship between unit processes within each module and between modules themselves. A seemingly “trivial” change in one unit process in a given module can have dramatic effects on processes in other modules. In other words, there is no such thing as a trivial process change.

CMOS Process Description

Even with a single-device type, process schemes vary with respect to achieving similar structures, so it would be virtually impossible to outline all schemes. However, an example of a generic (but representa- tive), deep-submicron CMOS process ﬂow is presented (“deep” indicates that a deep- or short- wavelength ultraviolet light source is used when patterning the wafers). Our generic CMOS technology will have the following features:

Following each major process step, cross sections will be shown. The cross sections were generated with a technology computer-assisted design (TCAD) package called Tsuprem-4 and Taurus-Visual (2D), released by Technology Modeling Associates, Inc. These tools simulate a deﬁned sequence of unit processes, allowing a process to be modeled before actually being implemented in a fabrication facility. For brevity, there are several omissions and consolidations in the process description. These include:

1. Wafer cleaning performed immediately before all thermal processes, metal depositions, and after photoresist removal.

opening in passivation

2. Individual photolithographic process steps (such as dehydration bake, wafer priming, photoresist application, softbake, alignment, exposure, photoresist development, hardbake, inspection, regis- tration measurement, and critical dimension [CD] measurement).

3. Backside ﬁlm removal following select CVD processes.

4. Metrology performed to measure particle levels and ﬁlm thickness, and post-etch CDs.

To implement our CMOS technology we will employ the use of a reticle set as outlined in Table 12.1. The masks are labeled as having either a clear or dark-ﬁeld. Clear-ﬁeld masks contain opaque features totaling <50% of the mask area. In contrast, dark-ﬁeld masks have opaque features accounting for >50% of the total area. Using this mask set, we will assume the exclusive use of positive-tone photoresist processing. When appropriate, representative mask features will be shown that will yield isolated, complementary transistors adjacent to one another.

FEOL Integration

As stated previously, the FEOL encompasses all processing required to fabricate the fully formed, isolated CMOS transistors. This subsection discusses the modules and unit processes required for a representative CMOS process ﬂow.

Starting Material

The choice of substrate is strongly inﬂuenced by the application and characteristics of the CMOS ICs to be fabricated. Bulk silicon is the least expensive, but may not be the optimal choice in high-performance or harsh-environment CMOS applications. Epitaxial (epi) wafers are heavily doped bulk wafers with a thin, moderately to lightly doped epitaxial silicon layer grown on the surface. The primary advantage of epiwafers is for immunity to latch-up. SOI wafers provide a performance increase and elimination of latch up. However, SOI CMOS is more costly to implement than the bulk or epitechnologies. The three general types of silicon substrates are shown in Figure 12.23.

In current manufacturing, wafer diameters typically range from 150 to 300 mm. Wafer thickness increases with diameter to allow for greater rigidity. The actual CMOS is constructed in the top 1 µm or less of the wafer; the remaining hundreds of micrometers are used solely for mechanical support during device fabrication.

We will use bulk silicon wafers for our CMOS technology in this section. It should be noted that, with relatively minor process and integration adjustments, our technology could be applicable to the epi or

SOI CMOS processes. Figure 12.24, the ﬁrst of many simulated cross sections, shows only the top 2 µm of silicon. At the beginning of the fabrication process, wafer characteristics such as resistivity, sheet resistance, crystallographic orientation, and bow-and-warp are measured and recorded. Each wafer receives its own number and lot assignment, usually inscribed with a laser.

STI-Module

Devices (e.g., PMOS and NMOS) must be electrically isolated from one another. This isolation is of primary importance. It suppresses current leakage between similar as well as dissimilar devices.

One of the simplest isolation methods is to fabricate the CMOS so that a reversed-bias pn junction is formed between the transistors. Oppositely doped regions (e.g., n well adjacent to a p well) can be electrically isolated by tying the n region to the most positive potential in the circuit and the p region to the most negative. As long as the reverse bias is maintained and the breakdown voltage is not exceeded for all operating conditions, only a small diode reverse-saturation current accounts for the leakage current. Because this junction leakage current is directly proportional to the size of the junction area, junction isolation alone is inadequate for the large p and n regions in modern devices.

The second general method of isolation is related to the formation of thick dielectric regions, called ﬁeld regions, between transistors. The region without the thick dielectric is where the transistors reside. It is called the active area. The relatively thick oxide that forms between active areas is called ﬁeld oxide (FOX). Polysilicon interconnections formed over the ﬁeld regions provide localized electrical continuity between transistors. This arrangement inherently leads to the formation of parasitic ﬁeld-effect transistors. The FOX increases the parasitic transistor’s threshold voltage sufﬁciently so that the device always remains in the off state. The parasitic transistor’s threshold voltage can be further enhanced by increasing the surface doping concentration, called channel stops, under the FOX. Two general approaches apply to the formation of FOX regions: local oxidation of silicon (LOCOS) and STI. LOCOS has been used extensively for 0.5 µm or larger minimum linewidth CMOS technologies. In LOCOS, a diffusion barrier of silicon nitride blocks the thermal oxidation of speciﬁc regions on the surface of a wafer. Both oxygen and water diffuse slowly through silicon nitride. Hence, nitride can be deposited and patterned to deﬁne active areas and FOX areas. The primary limitation to LOCOS is bird’s beak encroachment, where the lateral diffusion of the oxidant forms an oxide feature that in cross section resembles a bird’s beak. The bird’s beak encroaches into the active area, thereby reducing the achievable circuit-packing density. LOCOS also requires a long, high-temperature process, which can result in signiﬁcant diffusion of previously introduced dopants.

STI is the dominant isolation technology for sub-0.5 µm CMOS technologies. As the name implies, a shallow trench is etched into the surface of the wafer and then ﬁlled with a dielectric serving as the FOX. A typical STI process sequence is outlined below. From a processing perspective, STI is complex; however, it can be implemented with minimal active-area encroachment. Moreover, it has a relatively low thermal budget. The CMOS technology outlined in this chapter uses STI to achieve device isolation. The STI module begins with thermal oxidation of the surface of the wafer (Figure 12.25). The resultant oxide serves as a ﬁlm-stress buffer, called a pad oxide, between silicon and the subsequently deposited silicon nitride (Si3N4) layer. It will also be used after the post-CMP nitride strip as an ion implant sacriﬁcial oxide. Next,

Si3N4 is deposited on the oxidized wafer by LPCVD (Figure 12.26). This nitride will later serve as both an implant mask and a CMP stop layer.

Photolithography (Figure 12.27, mask layer 1) is used to produce the appropriate patterns in photoresist to deﬁne the active areas. Then endpoint detected RIE transfers the photoresist pattern into the underlying ﬁlm stack of nitride and oxide. Notice in Figure 12.27 that, under the photoresist, the PMOS and NMOS devices will be fabricated on the left and right side, respectively. The region cleared of photoresist corresponds to the isolation regions. Timed RIE forms 0.4 µm deep silicon trenches with the photoresist softmask present (Figure 12.28). Although the etching can proceed without the resist, the sidewall proﬁle can be tailored to a speciﬁc slope with the presence of the polymer during the etch process. Sloped sidewalls can help reduce leakage current from parasitic corner transistors, although at the cost of reduced packing density. Following the silicon etch, O2 plasma and wet processing strip the photoresist and etch by-products from the surface of the wafer. At this point, the general structural form of the STI is completed.

The subsequent series of processes improve the STI’s effectiveness in suppressing leakage currents. The expanded view of the trench (Figure 12.29) shows a thin oxide that has been thermally grown on the exposed silicon. It should be noted that the nitride provides a barrier to the diffusion of oxygen, hence the oxidation occurs only in the silicon-exposed regions. This oxide, which aids in softening the corner of the trench, will be used as a sacriﬁcial implant layer in the subsequent ion implantation. In general, such implant sacriﬁcial oxides are used to suppress ion channeling in the crystal lattice, minimize lattice damage from the ion bombardment, and protect the silicon surface from contamination. Photolithography (mask layer 2) is used to pattern resist to protect the PMOS sides of the trench during the p-wall implant. A shallow boron ﬂuoride (BF2) implant is performed to dope what will eventually become the. p-well trench sidewalls (called the p walls) (Figure 12.30). The p-wall implant increases the threshold voltage of the parasitic corner transistor and minimizes leakage under the trench. Then the BF2-implanted resist is stripped, using O2 plasma and wet processing (Figure 12.31). Again, photolithography (Figure 12.32, mask layer 3) is used to produce the complementary pattern for the n-wall implant. For the same reasons, this shallow phosphorus implant is introduced into what will become the n-well trench sidewalls. Next, the phosphorus-implanted resist is stripped, using O2 plasma and wet processing, yielding the structure depicted in Figure 12.33.

At this point, the sacriﬁcial oxide has been degraded by the implantations and is likewise stripped, using a buffered hydroﬂuoric acid (HF) solution. A thin, high-quality thermal oxide is regrown in the trenches to form what is called a trench liner. In general, the liner oxide improves the interface quality between the silicon and the subsequent trench ﬁll, thus suppressing the interface leakage current. Speciﬁcally, the formation of the trench liner oxide “cleans” the surface prior to trench fill, anneals sidewall implant damage, and passivates interface states to minimize parasitic leakage paths.

Once the liner oxide is grown, CVD overﬁlls the trenches with a dielectric (Figure 12.34). This trench ill provides the ﬁeld isolation that is required to increase the threshold voltage of the parasitic ﬁeld transistors. Further, it serves to block subsequent ion implants. Although, not shown, it is common to use a “block-out” pattern to improve the uniformity of the STI CMP. In Figure 12.35, CMP removes the CVD overﬁll. The nitride is used as a polish-stop layer. Next, a brief buffered oxide etch removes oxide that may have formed on top of the nitride. Then the nitride is removed from the active areas by using a wet- or dry-etch process (Figure 12.36). Note that the pad oxide remains after this step. At this point, the STI is fully formed.

Twin-Tub Module

CMOS can be implemented in four general forms: n well, p well, twin well (called twin tub), and triple well. The CMOS technology discussed in this chapter uses a twin-well approach. The p well and n well provide the appropriate dopants for the NMOS and PMOS, respectively. Modern wells are implanted with retrograde proﬁles to maximize transistor performance and reliability.

Following the STI module, the twin-tub module begins with p-well photolithography (mask layer 2, second use) to generate a resist pattern that covers the PMOS-active regions, but exposes the NMOS-active areas (Figure 12.37). A relatively high-energy boron implant is performed into the NMOS-active areas, but blocked from the PMOS-active area. The pad oxide remaining from the STI module now serves as the sacriﬁcial oxide for the well implants. It should be pointed out that the p well can be formed by a composition of several

implants at different doses and energies to achieve the desired retrograde proﬁle. Following the p-well implant, the resist is removed, using O2 plasma and wet processing, resulting in the structure shown in Figure 12.38.

Next, a complimentary resist pattern is formed using the n-well mask and photolithography (Figure 12.39, mask layer 3, second use). Again, a relatively high-energy implant, this time phosphorus, generates the n well. As with the p well, a multitude of implants may be used to achieve the desired retrograde proﬁle. Following the n-well implant, O2 plasma and wet processing strip the resist (Figure 12.40). At this point, both the isolation and wells are fully formed. Figure 12.41 shows the cross section of the substrate after the twin-tub module. Notice the net doping proﬁle is given, highlighting both the well and wall implants simultaneously. It should be emphasized that the PMOS are fabricated in the n wells while the NMOS are made in the p wells.

Gate Module

The gate module begins (Figure 12.42) with the buffered oxide etching of the remaining thin oxide in the active areas from the twin-tub module. A sacriﬁcial oxide is thermally grown to serve as a threshold- adjust implant oxide and a pregate oxidation “clean-up”. Next, a blanket (unpatterned), low-energy BF2 threshold adjust implant is done (Figure 12.43). It allows for the “tuning” of both the PMOS and NMOS threshold voltages. The single boron implant is common for single work-function gates. However, for dual work-function gates (common in technologies with minimum gate lengths of 250 nm or less),

separate p- and n-type implants are required for the threshold adjustment in the PMOS and NMOS, respectively.

The next set of processes form the “gate stack” (the gate dielectric and polysilicon gate electrode). Of course, the gate stack provides for capacitive coupling to the channel. The sacriﬁcial oxide is stripped by wet processing from the active areas. Then a high-quality, thin oxide is thermally grown to serve as the gate dielectric (Figure 12.44). In modern CMOS, it is common to use nitrided gate oxide by performing the oxidation in O2 and NO or N2O. It can be argued that the gate oxidation is the most critical step in the entire process sequence, because the characteristic of the resultant ﬁlm greatly determines the behavior of the CMOS transistors.

LPCVD polysilicon deposition immediately follows the gate oxidation (Figure 12.45). For single work- function gates, the polysilicon can be doped with phosphorus during polydeposition, or subsequently implanted. For dual work-function gates, the NMOS and PMOS can be doped during the n+ and p+ source/drain implants, respectively.

Once the gate stack is formed, the transistor gates and local interconnects are patterned using photo- lithography (mask layer 4) to generate the appropriate patterns in photoresist (Figure 12.46). The gate patterning must be precisely controlled, since it determines the gate lengths. Deviations in the resultant

physical gate lengths can cause severe performance issues with the CMOS. The ideal gate proﬁles following the RIE of polysilicon and subsequent stripping of the resist are seen in Figure 12.46.

The gate module concludes with polyreoxidation (Figure 12.47). Thermal oxidation of the polysilicon and active silicon facilitates the growth of a buffer pad oxide for the subsequent nitride spacer deposition and electrically activates the implanted dopants in the polysilicon. Since the polysilicon oxidizes at a faster rate than the crystalline silicon, the resultant oxide thickness is greater on the polysilicon than on the active silicon.

Source/Drain Module

At the onset of the source/drain module, a series of processes forms the source/drain extensions. Photolithography (Figure 12.48, mask layer 5) is used to pattern the resist so that the NMOS devices are exposed. Then a low-energy phosphorus implant forms the n-channel LDD (nLDD) extensions. The presence of the polysilicon gate inherently leads to the self-alignment of the extensions with respect to the gate. The nLDD suppresses hot-carrier injection into the gate and reduces short-channel effects in the NMOS. Often, at this point in the process sequence, a deep boron pocket implant is used to prevent source/drain punch-through in the NMOS. Finally, the photoresist is stripped, yielding the structure shown in Figure 12.49.

The p-channel source drain extensions are formed similarly. Photolithography (Figure 12.50, mask layer 6) protects NMOS devices with resist. Boron implanted at low energy creates the p-channel LDD (pLDD) extensions. Again, the polysilicon serves to self-align the implant with respect to the gate electrodes. As was the case with the NMOS, a deep phosphorus pocket implant will suppress punch- through in the PMOS. Finally, the photoresist is stripped (Figure 12.51).

To complete the source/drain extensions, the gate sidewall spacers must be formed prior to the actual source/drain implants. First, conformal silicon nitride (or an oxide) is deposited using LPCVD (Figure 12.52). Following a nitride etch, this nitride will form the LDD sidewall spacers. The spacers function as a mask to the source/drain implants and as a barrier to the subsequent salicide formation. The actual spacers are formed.

by an unpatterned anisotropic RIE of nitride (Figure 12.53). The spacer etch is end-pointed on the underlying oxide. Because the nitride is the thickest along the polysilicon sidewall, a well-formed insulating region remains on both sides of the polysilicon. This structure is called a spacer.

During source/drain implants, the polysilicon and spacers combine to block the implantation, thus allowing self-alignment for not only the gate but also for the LDD extensions. Stating this, the NMOS source/drains are formed (Figure 12.54). Photolithography (mask layer 5, second use) protects the PMOS with resist while exposing the NMOS. A relatively low-energy, high-dose arsenic implant is performed to form the n+ regions, and the resist is stripped (Figure 12.55). In addition to source/drain formation, this implant creates the necessary n+ ohmic contacts.

The PMOS source/drains and p+ ohmic contacts are formed in a similar manner by photolithography (mask layer 6, second use) and a low-energy, high-dose BF2 implant (Figure 12.56). Then the resist is stripped (Figure 12.57). The source/drain module concludes with a high-temperature anneal that electrically activates the implants and recrystallizes the damaged silicon. In modern CMOS, the primary reason for choosing polysilicon as the gate electrode material as opposed to metal is that polysilicon can withstand the high temperatures required to activate the source/drain implants.

At this point in our CMOS process sequence, we have fully formed the CMOS transistors and their isolation. This marks the completion of the FEOL. Figure 12.58 summarizes its main features.

BEOL Integration

CMOS process ﬂow continues through the BEOL. It encompasses all processes required to “wire” the transistors to one another and to the bond pads. CMOS requires several metal layers to achieve the interconnects required for modern designs. Following the processing through the ﬁrst two metal layers will provide an appreciation of the overall BEOL integration.

Self-Aligned Silicide (Salicide) Module

At the boundary of the FEOL and BEOL is the self-aligned silicide (called salicide) formation. Silicide lowers the sheet resistance of the polysilicon and active silicon regions. Salicide relies on the fact that metal silicide generally will not form over dielectric materials such as silicon nitride. Therefore, a metal such as titanium or cobalt can be deposited over the entire surface of the wafer and then annealed to selectively form silicide over exposed polysilicon and silicon. Because of the presence of the trench ﬁll and sidewall spacers, the silicide becomes self-aligned without the need for photopatterning.

The salicide module begins by removing the thin oxide, present from the FEOL, using buffered HF (Figure 12.59). Next, a refractory metal (e.g., titanium or cobalt) is deposited by sputtering (Figure 12.60). To minimize contamination, a thin layer of TiN is deposited as a cap. A relatively low-temperature, nitrogen-ambient, rapid thermal annealing (RTA) is used to react titanium (or cobalt) with the silicon, forming TiSi2 (or CoSix). The resultant silicide (e.g., C49) is a high-resistivity phase. Also, notice that the underlying nitride and oxide serve to block the formation of the silicide from the sidewalls and trenches, respectively.

To prevent spacer overgrowth of the silicide, the low-resistivity phase is achieved by processing with two separate anneals. The ﬁrst, described above, forms the high-resistivity phase without the risk of silicide formation on the nitride. The second, described below, occurs after wet chemical etching of the unreacted titanium (or cobalt) using a higher temperature. This causes a phase change (C49 to C54 for TiSi2) with a much lower resistivity. If one high-temperature anneal was originally performed to achieve the low-resistivity phase, then signiﬁcant overgrowth can occur, leading to current leakage from the source and drain to the gate of the transistors.

To continue the salicide module, following the ﬁrst anneal, the unreacted titanium (or cobalt) is wet-etched chemically from the wafer. The second RTA, in argon ambient at a slightly higher temperature, is used to achieve the low-resistivity phase (Figure 12.61).

Premetal Dielectric

The premetal dielectric (PMD) provides electrical isolation between metal1 and polysilicon or silicon. To aid the subsequent contact etching process, a thin layer of silicon nitride is deposited as an etch stop. This is followed by high-density plasma deposition of the PMD oxide (Figure 12.62). The resultant surface of the PMD must be planarized to allow for improved DOF for the subsequent high-resolution photo- patterning of metal1. CMPis used to planarize the PMD (Figure 12.63).

Contact Module

The contacts provide the electrical coupling between metal1 and polysilicon or silicon. The ﬁrst BEOL photolithography (mask layer 7) step is used to pattern contact openings in the resist. The PMD is then dry- etched, using the nitride as an etch-stop layer. The resist is then stripped from the wafer (Figure 12.64). Contact openings to the source and drains are shown; contacts to polysilicon over FOX are formed at the same time, but are not shown.

Next, a thin layer of titanium is deposited by ionized metal plasma deposition, preceded by an in-situ argon sputter etch to clean the bottom of the high-aspect ratio contact openings. The titanium is the ﬁrst component of the contact liner. It functions to chemically reduce oxides at the bottom of the contacts. The second component of the liner is a thin CVD TiN. This layer’s primary purpose is to act as a diffusion barrier to ﬂuorine (which readily etches silicon) that will be used in the subsequent tungsten deposition. The contact openings are ﬁlled (actually overﬁlled) with tungsten using a tungsten ﬂuoride (WF6) CVD process (Figure 12.65). Then, using CMP, the overﬁlled tungsten is polished back to the top of the planarized PMD (Figure 12.66). At this point, the surface of the wafer is ultrasmooth and essentially free of all topography. To aid the photolithographic alignment of the metal layer to the contacts, a tungsten recess etch is performed. The recessed contacts are shown in Figure 12.67.

Metallization 1

To allow for electrical signal transmission from contact-to-contact and from contact-to-via1, deﬁned met- allization must be formed. Following the recess etch, sputtering deposits a ﬁlm stack consisting of Ti/TiN/ Al/TiN (Figure 12.68). The Ti provides adhesion of the TiN and reduces electromigration problems. The bottom TiN serves primarily as a diffusion barrier to TiAl3 formation. The topmost TiN acts as an antire- ﬂective coating for the metal photolithography as well as an etch stop for the subsequent via formation.

Photolithography (mask layer 8) is used to generate the metal1 pattern in the resist (Figure 12.69). A dry-metal etch transfers the pattern into the metal. To prevent metal corrosion, the resist is plasma stripped in an O2/N2/H2O ambient (Figure 12.69).

Note that this is not a discussion of metal implementation using copper. Copper wiring is often implemented with dual-Damascene techniques, where vias and metal layers are simultaneously formed in a series of process steps.

Intrametal Dielectric 1 Deposition

The intrametal dielectric 1 (IMD1) provides the electrical isolation between metal1 and metal2. This ﬁlm usually is deposited using high-density plasma CVD (Figure 12.70). The conformal deposition results in surface topography that must be planarized by CMP to improve the DOF for subsequent photolithographic steps, as in the case of PMD planarization.

Via1 Module

Electrical coupling between metal 1 and metal 2 is achieved by the via1 module. The planarized IMD is photolithographically deﬁned (mask layer 9) and an RIE is used to open the vias. The resist is stripped using O2 plasma and wet processing (Figure 12.71). Next, as with the contact ﬁll, in the step of argon sputter etch followed by deposition of thin layers of IMP titanium and CVD TiN. A WF6 CVD process is used to deposit (overﬁll) the vias (Figure 12.72). The excess tungsten is removed by CMP, using the IMD1 as a “polish stop” (Figure 12.73). Again, to provide observable alignment features, a tungsten recess etch is often required (Figure 12.73).

Metallization 2

In a manner similar to the metal1 process, the metal2 stack is deposited (Figure 12.74) and photolitho- graphically defined (Figure 12.75, mask layer 10).

Additional Metal/Dielectric Layers

At this point, additional tiers of dielectric/metal layers can be formed by replicating the aforementioned processes. In modern CMOS, the number of metal layers can be greater than eight. It should be noted

that as dielectric/metal layers are added, the cumulative ﬁlm stresses may cause signiﬁcant bow/warp in the wafers. Hence, great effort is expended tominimize stresses in the BEOL ﬁlms.

Final Passivation

To protect the CMOS from mechanical abrasion during probe and packaging, and to provide a barrier against contaminants (e.g., H2O and ionic salts), a ﬁnal passivation layer must be deposited. The passi- vation type is determined in large part by the CMOS ICs’ packaging. Common passivation layers are doped glass and silicon nitride on deposited oxide. Figure 12.76 shows the resultant cross-section of our CMOS process ﬂow after deposition of the passivation. Finally, the bond pads are opened with photoli- thography (mask layer n) and dry etching the passivation. The CMOS is completed with a resist strip (Figure 12.77).

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