CMOS Fabrication:Back-End Processes and Summary of CMOS Fabrication.

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Back-End Processes

After final passivation, the wafers are removed from the clean room in preparation for a series of back-end (i.e., post-fab) processes. These processes include wafer probe, die separation, packaging, and final test/burn-in.

Wafer Probe

Generally, dedicated die with parametric structures and devices are stepped into various positions of the wafer. Alternatively, parametric structures are placed in the dividing regions, called streets or scribe lines, between the die. Electrical characterization of these parametric structures and devices is often performed at select points in the fabrication process flow (such as after metal1 patterning). Parameters such as contact resistance, sheet resistance, transistor threshold voltage, saturated drain current, off-current, subthreshold slope, etc., are measured. If problems are observed from the in-line parametric tests, troubleshooting can begin sooner than if testing is only performed after final passivation. Furthermore, wafers that do not meet parametric standards can be removed (or “killed”) from the fabrication sequence (thus saving money).

After the completed wafers are removed from the fab, wafer-level probing is performed to check the final device parameters and CMOS IC functionality and performance. Wafer probe is accomplished by using sophisticated testers that can probe individual die (or sets of die) and apply test vectors to determine circuit behavior. Inevitably, a percentage of die will not pass all the vector tests and are thus considered failed. The ratio of good die to total die represents the wafer yield given by

Y = Number of die passing all tests/total number of die (12.13) In these cases, the die are marked, often with an ink dot, to indicate a nonfunctional circuit. Since the

processing costs of a wafer are fixed, higher yield equates to higher profit.

Die Separation

Before separating individual die, the backs of the wafers are often thinned using a lapping process similar to the CMP discussed in Section 12.1.5. This thinning may be required for specific types of packages. It can also help remove heat from the CMOS circuits.

Next, the die are separated from the wafers using a dicing saw (a diamond-coated blade). The cutting paths are aligned to the streets or scribe lines on the wafer. Great care is given to minimize damage to the die during this mechanical separation process. Along with the inked die, those with observable damage from dicing are discarded. Obviously, the separation process can reduce the yield.

Packaging

The good die are attached to a header in the appropriate package type by either eutectic attachment or epoxy attachment. Next, the bond pads are wired to the leads of the package. Common wire-bonding techniques include thermocompression, thermosonic, and ultrasonic bonding. From this point, packaging is completed by a wide range of different processes, depending on the kind of package the IC will reside in. For instance, in plastic, dual in-line packages, a process similar to injection molding is performed, creating a relatively inexpensive package. If ceramic packaging is required, the attached and wire-bonded die will reside in a cavity sealed by a metal lid. In general, plastic (or epoxy) packages are inexpensive, but do not provide a hermetic seal, while ceramic packages are more costly, but do provide a hermetic seal. For information on other packaging schemes, see Further Reading at the end of this chapter. Finally, it should be noted that the packaging process can add to the overall yield loss.

Final Test and Burn-In

Once packaged, the CMOS parts are tested for final functionality and performance. After this is done, it is common for the parts to go through a burn-in step in which they are operated at extreme temperatures and voltages to weed out infant failures. Additional yield loss can be observed.

Summary

In this chapter, the fundamental unit processes required for manufacturing CMOS ICs were introduced. These unit processes included thermal oxidation, solid-state diffusion, ion implantation, photolithography, wet chemical etching, dry (plasma) etching, CMP, PVD, and CVD. A brief overview of substrate preparation was also given. Following this foundation, a representative, deep-submicron CMOS process flow was described and the significant issues in both FEOL and BEOL integration were discussed. Finally, an overview of the back-end processes was presented, including wafer probe, die separation, packaging and final test, and burn-in.

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