Bipolar Technology:High-Performance Bipolar Technology

High-Performance Bipolar Technology

The development of a high-performance bipolar technology for ICs signified a large step forward, both with respect to speed and packing density of bipolar transistors. A representative device cross section of a so-called double-poly transistor is depicted in Figure 1.10. The important characteristics for this bipolar technology are the polysilicon emitter contact, the advanced device isolation, and the self-aligned struc- ture. These three features are discussed here with an emphasis on self-alignment where the two basic process flows are outlined—the single- and double-poly transistor.

Polysilicon Emitter Contact

The polysilicon emitter contact is fabricated by a shallow diffusion of n-type species (usually arsenic) from an implanted n+-polysilicon layer into the silicon substrate [58] (see emitter region in Figure 1.10). The thin oxide sandwiched between the poly- and monosilicon is partially or fully broken up during contact formation. The mechanism behind the improved current gain is strongly related to the details

of the interface between the polysilicon layer and the monosilicon substrate [48]. Hence, the cleaning procedure of the emitter window surface before polysilicon deposition must be carefully engineered for process robustness. Otherwise, the average current gain from wafer to wafer will exhibit unacceptable variations. The emitter window preparation and subsequent drive-in anneal conditions can also be used in tailoring the process with respect to gain and emitter resistance.

From a fabrication point of view, there are further advantages when introducing polysilicon emitter technology. By implanting into the polysilicon rather than into single-crystalline material, the total defect generation as well as related anomalous diffusion effects are strongly suppressed in the internal transistor after the drive-in anneal. Moreover, the risk of aluminum spiking during the metallization process, causing short-circuiting of the pn junction, is strongly reduced compared with the conventional contact formation. As a result, some of the yield problems associated with monosilicon emitter fabrication are, to a large extent, avoided when utilizing polysilicon emitter technology.

Advanced Device Isolation

With advanced device isolation, one usually refers to the deep trenches combined with LOCOS or shallow trenches [59] as seen in Figure 1.10. Before trench etching the collector region has been formed by a buried- layer implantation followed by epitaxy or a double-epitaxial layer (n+–n) grown on a much lower doped p– substrate. The deep trench must reach below the buried layer, meaning a high-aspect ratio reactive-ion etch. Hence, the trenches will define the lateral extension of the buried-layer collector for the transistor.

The main reason for introducing advanced isolation in bipolar technology is the need for a compact chip layout. Quite naturally, the bipolar isolation technology has benefited from the trench capacitor development in the MOS memory area. The deep-trench isolation allows bipolar transistors to be designed at the packing density of VLSI.

The fabrication of a deep-trench isolation includes deep-silicon etching, channel-stop p+ implantation, an oxide/nitride stack serving as isolation, intrinsic polysilicon fill-up, planarization, and cap oxidation [60]. The deep-trench isolation is combined with a LOCOS or shallow-trench isolation, which is added before or after deep-trench formation. The most advanced isolation schemes take advantage of shallow-trench isolation rather than ordinary LOCOS after the deep-trench process; in this way, a very planar surface with no oxide lateral encroachment (“birds beak”) is achieved after the planarization step. The concern regarding stress-induced crystal defects originating from trench etching requires careful attention so as not to seriously affect yield.

Self-Aligned Structures

Advanced bipolar transistors are based on self-aligned structures made possible by polysilicon emitter technology. As a result, the emitter-base alignment is not dependent on the overlay accuracy of the lithography tool. The device contacts can be separated without affecting the active device area.

The self-aligned structures are divided into single-polysilicon (single-poly) and double-polysilicon (double-poly) architectures, as visualized in Figure 1.11 [61]. The double-poly structure refers to the emitter polysilicon and base polysilicon electrode, whereas the single-poly only refers to the emitter polysilicon. From Figure 1.11, it is seen that the double-poly approach benefits from a smaller active area than the single-poly one, manifested in a reduced base-collector capacitance. Moreover, the double-poly transistor in general exhibits a lower base resistance. The double-poly transistor, however, is more complex to fabricate than the single-poly device. On the other hand, by applying inside spacer technology for the double-poly emitter structure, the lithography requirements are not as strict as in the single-poly case, where more conventional MOS design rules are used for definition of the emitter electrode.

Single-Poly Structure

The fabrication of a single-poly transistor has been presented in several versions, more or less similar to the traditional MOS flow. An example of a standard single-poly process is shown in Figure 1.12 [62]. After arsenic emitter implantation (Figure 1.12[a]) and polysilicon patterning, a so-called base link is implanted using boron ions (Figure 1.12[b]). Oxide is then deposited and anisotropically etched to form outside spacers, followed by the heavy extrinsic base implantation (Figure 1.12[c]). Shallow junctions (including emitter diffusion) are formed by rapid thermal annealing (RTA). A salicide or polycide metallization completes the structure (Figure 1.12[d]).

Another variation of the single-poly architecture is the so-called quasi-self-aligned process (see Figure 1.13) [63]. A base oxide is formed by thermal oxidation in the active area and an emitter window

is opened (Figure 1.13[a]). Following intrinsic base implantation, the emitter polysilicon is deposited, implanted, and annealed. The polysilicon emitter pedestal is then etched out (Figure 1.13[b]). The extrinsic base process, junction formation, and metallization are essentially the same as in the single- poly process shown in Figure 1.13. Note that in Figure 1.13, the emitter-base formation is self-aligned to the emitter window in the oxide, not to the emitter itself, hence explaining the term “quasi-self-aligned.” As a result, a higher total base resistance is obtained compared with the standard single-poly process.

The boron implantation illustrated in Figure 1.12(b) is an example of the so-called base-link engi- neering aimed at securing the electrical contact between the heavily doped p+-extrinsic base and the much lower doped intrinsic base. A poor base link will result in high total base resistance, whereas a base link with a too strong diffusion may create a lateral emitter-base tunnel junction leading to nonideal base current characteristics [64]. Furthermore, a poorly designed base link jeopardizes matching between individual transistors since the final current gain may vary substantially with the emitter width.

Double-Poly Structure

The double-poly structure originates from the classical IBM structure presented in 1981 [65]. Most high- performance commercial processes today are based on double-poly technology. The number of variations are less than for the single-poly one, mainly with different aspects on base-link engineering, spacer technology, and SIC formation. One example of a double-poly fabrication is presented in Figure 1.14. After deposition of the base polysilicon and oxide stack, the emitter window is opened (Figure 1.14[a]) and thermally oxidized. During this step, p+ impurities from the base polysilicon diffuse into the monosilicon, thus forming the extrinsic base. In addition, the oxidation repairs the crystal damage caused by the dry etch when opening the emitter window. A thin silicon nitride layer is then deposited, the intrinsic base is implanted using boron, followed by the fabrication of amorphous silicon spacers inside the emitter window (Figure 1.14[b]). The nitride is exposed to a short dry etch, the spacers are removed, and the thin oxide is opened up by an HF dip. Deposition and implantation of the polysilicon emitter film is carried out (Figure 1.14[c]). The structure is patterned and completed by RTA emitter drive-in and metallization (Figure 1.14[d]). The emitter will thus be fully self-aligned with respect to the base. Note that the inside spacer technology implies that the actual emitter width will be significantly less than the drawn emitter width. The definition of the polyemitter in the single- and double-poly process leads to some overetching into the epilayer; see Figure 1.12(b) and Figure 1.14(a), respectively. This can be alleviated by inserting, for example, a thin thermal oxide as an etch-stop layer. After emitter patterning this oxide can be removed by a short wet etch, selective to the underlying silicon. This situation is of no concern for the quasi-self-aligned process where the etch of the polysilicon emitter stops on the base oxide.

Also, vertical pnp bipolar transistors based on the double-poly concept have been demonstrated [66]. Either boron or BF2 is used for the polyemitter implantation. A pnp device with an fT of 35 GHz has been presented in a classical double-poly structure [67].