Bipolar Technology:Bipolar Process Design

Bipolar Process Design

The design of a bipolar process starts with the specification of the application target and its circuit technology (digital or analog). This leads to a number of requirements formulated in device parameters and associated figures of merit. These are mutually dependent, and a parameter trade-off must therefore be made, making the final bipolar process design a compromise between various conflicting device requirements.

Figures of Merit

In the digital bipolar process, the cutoff frequency (fT) is a well-known figure of merit for speed. The fT is defined for a common-emitter configuration with its output short circuit when extrapolating the small signal current gain to unity. From a circuit perspective, a more adequate figure of merit is the gate delay time (td) measured for a ring-oscillator circuit containing an odd number of inverters [10]. The td can be expressed as a linear combination of the incoming time constants weighted by a factor determined by the circuit topology (e.g., ECL) [10, 11]. Alternative expressions for td calculations have been proposed [12]. Besides speed, power dissipation can also be a critical issue in densely packed bipolar digital circuits, resulting in the power-delay product as a figure of merit [13].

In the analog bipolar process, the DC properties of the transistor are of utmost importance. This involves minimum values on common-emitter current gain (β), Gummel plot linearity (βmax/β) break- down voltage (BVCEO), and early voltage (VA). The product β × VA is often introduced as a figure of merit for the device DC characteristics [14]. Rather than fT , the maximum oscillation frequency FMAX =FT (8πRBCBC ), is preferred as a figure of merit in high-speed analog design, where RB and CBC denote the total base resistance and the base-collector capacitance, respectively [15]. Alternative figures of merit for speed have been proposed in the literature [16, 17]. Analog bipolar circuits are often crucially dependent on a certain noise immunity, leading to the introduction of the corner frequency and noise figure as figures of merit for low-frequency and high-frequency noise properties, respectively [18].

Process Optimization

The optimization of the bipolar process is divided between the intrinsic and extrinsic device design. This corresponds to the vertical impurity profile and the horizontal layout of the transistor, respectively [10]; see example in Figure 1.2, where the device cross section is also included. It is clear that the vertical profile and horizontal layout are primarily dictated by the given process and lithography constraints, respectively.

Figure 1.3 shows a simple flowchart of the bipolar design procedure. Starting from the specified DC parameters at a given bias point, the doping profiles can be derived. The horizontal layout must be adjusted for minimization of the parasitics. A (speed) figure of merit can then be calculated. An implicit relation is thus obtained between the figure of merit and the processing parameters [11, 19]. In practice,

several iterations must be performed in the optimization loop to find an acceptable compromise between the device parameters. This procedure is substantially alleviated by one- or two-dimensional process simulations of the device fabrication as well as finite-element physical device simulations of the bipolar transistor [20, 21]. For optimization of a large number of device parameters, the strategy is based on screening out the unimportant factors, combined with a statistical approach (e.g., response surface methodology) [22, 23].

Vertical Structure

The engineering of the vertical structure involves the design of the collector, base, and emitter impurity profiles. In this respect, fT is an adequate parameter to optimize. For a modern bipolar transistor with suppressed parasitics, the maximum fT is usually determined by the forward transit time of minority carriers through the intrinsic component. The most important fT trade-off is against BVCEO , as stated by the Johnson limit for silicon transistors [24], the product fT × BVCEO cannot exceed 200 GHz V. A more detailed calculation taking into account realistic doping profile predicts values of >500 GHz V) [25]. In

fact, recent experimental results for high-speed SiGeC bipolar transistors have shown a value of 510 GHz V for a 300 GHz fT technology with 1.7 V BVCEO [26].

Collector Region

The vertical n-type collector of the bipolar device in Figure 1.2 consists of two regions below the p-type base diffusion: a low or moderately doped n-type epitaxial (epi) layer, followed by a highly doped n+ subcollector. The thickness and doping level of the subcollector are noncritical parameters; a high arsenic or antimony doping density between 1019 and 1020 cm–3 is representative, resulting in a sheet resistance of 20–40 Ω/sq. In contrast, the design of the epilayer constitutes a fundamental topic in bipolar process optimization.

To first-order, the collector doping in the epilayer is determined by the operation point (more specif- ically, the collector current density) of the component (see Figure 1.3). A normal condition is to have the operation point corresponding to maximum fT, which typically means a collector current density of the order of 2–4 × 104 A/cm2. As will be recognized later, bipolar scaling results in increased collector current densities. Above a certain current level, there will be a rapid roll-off in current gain and cutoff frequency. This is due to high-current effects, primarily the base pushout or Kirk effect, leading to a steep increase in the forward transit time [27]. Since the critical current value is proportional to the collector doping [28], a minimum impurity concentration for the epilayer is required, thus avoiding fT degradation (typically around 1017 cm–3 for a high-speed device). Usually, the epilayer is doped only in the intrinsic structure by a selectively implanted collector (SIC) procedure [29]. An example of such a doping profile from an advanced 0.25 µm BiCMOS technology is seen in Figure 1.4. Such a collector design permits an improved control over the base-collector junction, that is, shorter base width as well as suppressed Kirk effect. The high collector doping concentration, however, may be a concern for both CBC and BVCEO . The latter value will therefore often set a higher limit on the collector doping value.

The SIC technology provides a simple way of creating a high-BVCEO device by masking the implantation. The reduced collector doping in the SIC-free device will also reduce the pinch-base resistance and

The preferred profile to achieve a good compromise between a too high field at the base-collector junction and suppression of the Kirk effect at high current densities is obtained by a retrograde collector profile [30]. For this profile the SIC implantation energy is chosen to obtain a low impurity concentration near the base-collector junction and then increasing toward the subcollector.

The thickness of the epilayer exhibits large variations among different device designs, extending several micrometers in depth for analog bipolar components, whereas a high-speed digital design typically has an epilayer thickness around 1 µm or below, thus reducing the total collector resistance. As a result, the transistor breakdown voltage is sometimes determined by reach-through breakdown (i.e., full depletion of penetration of the epicollector). The thickness of the collector layer can therefore be used as a parameter in determining BVCEO , which in turn is traded off against fT .

In cases where fmax is of interest, the collector design must be carefully taken into account. Compared with fT , the optimum fmax is found for thicker and less doped collector epilayers [32, 33]. The vertical collector design will therefore, to a large extent, determine the trade-off between fT and fmax.

Base Region

The width and peak concentration of the base profile are two of the most fundamental parameters in vertical profile design. In a conventional Si bipolar process the base width is limited by the implantation energy and to some extent the collector doping, since an implanted profile will have a Gaussian tail toward the collector. The base width WB is normally in the range 0.1–1 µm, whereas a typical base peak concentration lies between 1017 and 1018 cm–3. In contrast to this, base widths of <100 Å [34] with peak doping close to 1020 cm–3 can be achieved by SiGe epitaxy including a small amount of carbon for added profile control. The integral of the base doping over the base width is known as the Gummel number. The current gain of the transistor is determined by the ratio of the Gummel number in the emitter and base. In an SiGe transistor, the current gain is also strongly (exponentially) dependent on the Ge concentration in the base and therefore a higher base doping can be used without sacrificing gain. Usually, a current gain of at least 100 is required for analog bipolar transistors, whereas in digital applications, a β value around 20 is often acceptable. A normal base sheet resistance (or pinch resistance) for conventional bipolar processes is of the order of 100 Ω/sq, whereas the number for high-speed devices (implanted or epitaxial base) typically is in the interval 1 to 10 kΩ/sq [3]. This is due to the small WB (<0.1 µm) necessary for a short base transit time. However, a too narrow base will have a negative impact on fmax because of its RB dependence. As a result, fT and fmax exhibit a maximum when plotted against WB [35] or base doping [36].

The base impurity concentration must be kept high enough to avoid punch-through at low collector voltages; that is, the base-collector depletion layer penetrates across the neutral base. In other words, the base doping level is also dictated by the collector impurity concentration. Punch-through is the ultimate consequence of base width modulation or the early effect manifested by a finite output resistance in the IC–VCE transistor characteristic [37]. The associated VA or the product β × VA serves as an indicator of the linear properties for the bipolar transistor. The VA is typically at a relatively high level (>30 V) for analog applications, whereas digital designs often accept relatively low VA (<15 V).

A limiting factor for high base doping numbers above 5 × 1018 cm–3 is the onset of forward-biased tunneling currents in the emitter-base junction leading to nonideal base current characteristics [38]. Since the tunneling current is dependent on mid-bandgap states induced by process steps such as implantation, significantly lower tunneling has been reported for epitaxial base devices [39]. Therefore, base dopings well above 1019 cm–3 can be used in SiGe HBTs, with no significant nonideality observed in the base current.

The shape of the base profile has some influence on the device performance. The final base profile is the result of an implantation and diffusion process and, normally, only the peak base concentration is given along with the base width. Nonetheless, there will be an impurity grading along the base profile (see Figure 1.2 and Figure 1.4), creating a built-in electrical field and thereby adding a drift component for the minority carrier transport [40]. For very narrow base transistors, the uniform doping profile is preferable when maximizing fT [41, 42]. This is also valid under high injection conditions in the base [43]. Uniformly doped base profiles are common in advanced bipolar processes using epitaxial techniques for growing the intrinsic base.

Emitter Region

The conventional metal-contacted emitter is characterized by an abrupt arsenic or phosphorus profile fabricated by direct diffusion or implantation into the base area (see Figure 1.2) [44]. In keeping emitter efficiency close to unity (and thus high current gain), the emitter junction cannot be made too shallow (~1 µm). The emitter doping level lies typically between 1020 and 1021 cm–3 close to the solid solubility limit at the silicon surface, hence providing a low emitter resistance as well as a large emitter Gummel number required for keeping current gain high. Bandgap narrowing, however, will be present in the emitter, causing a reduction in the efficient emitter doping [45].

When scaling bipolar devices, the emitter junction must be made shallower to ensure a low emitter- base capacitance. When the emitter depth becomes less than the minority carrier recombination length, the current gain will inevitably degrade. This precludes the use of conventional emitters in a high- performance bipolar technology. Instead, polycrystalline (poly) silicon emitter technology is utilized. By diffusing impurity species from the polysilicon contact into the monocrystalline (mono) silicon, a very shallow junction (<0.2 µm) is formed; yet gain can be kept at a high level and even traded off against a higher base doping [46]. A gain enhancement factor between 3 and 30 for the polysilicon compared with the monosilicon emitter has been reported (see also Section 1.4) [47, 48].

Horizontal Layout

The horizontal layout is carried out to minimize the device parasitics. Figure 1.5 shows the essential parasitic resistances and capacitances for a schematic bipolar structure containing two base contacts. The various RC constants in Figure 1.5 introduce time delays. For conventional bipolar transistors, such parasitics often limit device speed. In contrast, the self-alignment technology applied in advanced bipolar transistor fabrication allows for efficient suppression of the parasitics.

In horizontal layout, fmax serves as a first-order indicator in the extrinsic optimization procedure because of its dependence on CBC and (total) RB. These two parasitics are strongly connected to the geometrical layout of the device. The more advanced td calculation takes all major parasitics into account under given load conditions, thus providing good insight into the various time delay contributions of a bipolar logic gate [49].

From Figure 1.5, it is seen that the collector resistance is divided into three parts. Apart from the epilayer and buried layer previously discussed, the collector contact also adds a series resistance. Provided the epilayer is not too thick, the transistor is equipped with a deep phosphorus plug from the collector contact down to the buried layer, thus reducing the total RC.

As illustrated in Figure 1.5, the base resistance is divided into intrinsic (RBi) and extrinsic (RBx) components. The former is the pinch-base resistance situated directly under the emitter diffusion, whereas the latter constitutes the base regions contacting the intrinsic base. The intrinsic part decreases with the current owing to the lateral voltage drop in the base region [50]. At high current densities, this causes current crowding effects at the emitter diffusion edges. This results in a reduced onset for high-current effects in the transistor. The extrinsic base resistance is bias independent and must be kept as small as possible (e.g., by utilizing self-alignment architectures). By designing a device layout with two or more base contacts surrounding the emitter, the final RB is further reduced at the expense of chip area. Apart from enhancing fmax, the RB reduction is also beneficial for device noise performance.

The layout of the emitter is crucial since the effective emitter area defines the intrinsic device cross section [51]. The minimum emitter area, within the lithography constraints, is determined by the operational collector current and the critical current density, where high-current effects start to occur [52]. Eventually, a trade-off must be made between the base resistance and device capacitances as a function of emitter geometry; this choice is largely dictated by the device application. Long, narrow emitter stripes, meaning a reduction in the base resistance, are frequently used. The emitter resistance is usually non- critical for conventional devices; however, for polysilicon emitters, the emitter resistance may become a concern in very small-geometry layouts [53].

Of the various junction capacitances in Figure 1.5, the collector-base capacitance is the most significant. This parasitic is also divided into intrinsic (CBCi) and extrinsic (CBCx) contributions. Similar to RBx, the CBCx

is kept low by using self-aligned schemes. For example, the fabrication of an SIC causes an increase only in CBCi, whereas CBCx stays virtually unaffected. The collector-substrate capacitance CCS is one of the minor contributors to fT; the CCS originates from the depletion regions created in the epilayer and under the buried layer. CCS will become significant at very high frequencies owing to substrate coupling effects [54].