Bipolar Junction Transistor Amplifiers:Compound Stage Building Blocks for IC Amplifiers.

Compound Stage Building Blocks for IC Amplifiers

Several of the single stages of the previous section can be combined to construct high-performance two- stage building blocks.

The Cascode Amplifier Stage

One of the problems with the common-emitter stage using an active load is the Miller effect. This stage has a high voltage gain from base to collector. The circuit of Figure 23.8 has an inverting voltage gain, AMB, that can be quite high, perhaps -700 V/V. The base–collector junction capacitance is multiplied by (1 + |AMB |) and reflected to the input loop. This capacitance adds to the diffusion capacitance from point b' to point e and can lower the upper corner frequency to a relatively small value.

In contrast, the common-base stage of Figure 23.10 has essentially no Miller effect, but has a low input impedance and can load the impedance of the driving source. The cascode stage combines the best features of both the common-emitter and common-base stages. The cascode amplifier stage of Figure 23.13 minimizes the capacitance reflected to the input. The input impedance to the circuit is that of the common-emitter stage and is two orders of magnitude higher than the common-base stage. In this circuit, the input capacitance is primarily composed of the diffusion capacitance of Q1. The voltage gain from base-to-collector of Q1 is quite low since the collector load of this device consists

of the impedance looking into the emitter of Q2. This impedance is approximately equal to the base- emitter diode resistance of Q2 which is

With low voltage gain, the Miller effect of the first stage is minimized. The upper device passes the incremental signal current of Q1 to its collector and develops a large voltage across the current source impedance. There is no Miller multiplication of capacitance from the input of Q2 (emitter) to the output (collector) since the gain is noninverting and negligible capacitance exists between emitter and collector. Thus, the cascode stage essentially eliminates Miller effect capacitance and its resulting effect on upper corner frequency.

A high-frequency equivalent circuit of this stage is shown in Figure 23.14. The resistance R includes any generator resistance and the base resistance, rx1 of Q1. The resistance rcs is the output resistance of the current source. The output capacitance is the sum of Cµ2, Ccs2, and any capacitance at the current source output. The resistance rout2 can be quite large since Q2 sees a large emitter resistance looking into the collector of Q1. This emitter load leads to negative feedback that increases the output resistance of Q2.

The midband voltage gain is calculated from the equivalent circuit of Figure 23.14 after eliminating the capacitors. This gain is found rather easily by noting that the input current to Q1 is

This current will be multiplied by b1 to become collector current in Q1. This current also equals the emitter current of Q2. The emitter current of Q2 is multiplied by a2 become collector current of Q2. The output voltage is then

where R3 = rout2 || rcs. This resistance could be very large if the current source resistance, rcs, is large. The value of rout2 will be high since the emitter of Q2 sees a resistance of rce1. Combining this information results in a midband voltage gain of

The Differential Stage

The differential pair or differential stage is very important in the electronic field. Virtually every op amp chip includes a differential pair as the input stage. Some advantages of the differential stage are its relative

immunity to temperature effects and power supply voltage changes, and its ability to amplify DC signals. The differential amplifier uses a pair of identical stages connected in a configuration that allows the temperature drift of one stage to cancel that of the other stage. The basic configuration of a differential stage is shown in Figure 23.15. The two devices can be connected and operated in several different configurations. The mode of operation most often used with the differential amplifier is the differential input–double-ended output mode. Differential input refers to a situation wherein the voltage appearing across the input of one stage is equal in magnitude, but opposite in polarity to the voltage appearing across the input of the other stage. Double-ended output refers to the fact that the output voltage is taken as the difference in voltage between the output voltage of each stage. In single-stage amplifiers, the output voltage appears between the circuit output and ground. This is called a single-ended output. In Figure 23.15, the double-ended output voltage is

depending on the choice of output terminals. If this differential pair used a single-ended output, it could be taken between the output of stage 1 and ground or the output of stage 2 and ground.

A second input mode that could be used is the common mode. If the same signal is applied to both inputs, the circuit is said to operate in common mode. If the amplifier stages have exactly equal gains, the signals vo1 and vo2 will be equal. The double-ended output signal would then be zero in the ideal differential stage operating in common mode. In practice the two amplifier gains will not be identical; thus, the common mode output signal will have a small value. The common-mode gain ACM is defined as

where AD is the differential voltage gain of the amplifier with a double-ended output. If the double- ended output had been defined as vo2 - vo1 rather than vo1 - vo2, then only the algebraic sign of AD would change.

In the general case, both common-mode and differential signals will be applied to the amplifier. This situation arises, for example, when the differential inputs are driven by preceding stages that have an output consisting of a DC bias voltage and an incremental signal voltage.

Using superposition, the output voltage for this case can be calculated from

The larger the CMRR, the smaller is the effect of ACM on the output voltage compared with AD.

A big advantage of the differential stage is in the cancellation of drift at the double-ended output.

Temperature drifts in each stage are often common-mode signals. For example, the change in forward voltage across the base–emitter junction with constant current is about -2 mV/°C. As the temperature changes, each junction voltage changes by the same amount. These changes can be represented as equal voltage signals applied to the two inputs. If the stages are closely matched, very little output drift will be noted. The integrated differential amplifier can perform considerably better than its discrete counterpart since component matching is more accurate and a relatively uniform temperature prevails throughout the chip. Power supply noise is also a common-mode signal and has little effect on the output signal if the common-mode gain is low.

As previously mentioned, the mode of operation most often used with the differential amplifier is the differential input, double-ended output mode. In this configuration, the input voltage applied to one stage should be equal in magnitude, but opposite in polarity to the voltage applied to the other stage. One method of obtaining these equal magnitude, opposite polarity signals using only a single input source is shown in Figure 23.16.

If the input resistances of both stages are equal, half of vin will drop across each stage. While the voltage from terminal a to terminal b of stage 1 represents a voltage drop, the voltage across the corresponding terminals of stage 2 represents a rise in voltage. We can write

Small-Signal Voltage Gain

Figure 23.18 represents a simple equivalent circuit for the BJT differential pair. The steps in calculating the single-ended or double-ended voltage gain of a differential pair are

1. Calculate the input current as iin = vin/Rin.

2. Note that the base currents are related to iin by ib1 = iin and ib2 = -iin.

3. Calculate collector currents as ic1 = b1ib1 and ic2 = b2ib2.

4. Calculate collector voltages from vo1 = -icRCeq1 and vo2 = -i2RCeq2, where RCeq = RC ïïrout (23.42)

With these values, the single-ended or double-ended voltage gain can be found. In the normal situation, we assume perfectly symmetrical pairs with b1 = b2 = b and RC1 = RC2 = RC. We also assume that the bias current I splits equally between the two stages giving IE1 = IE2 = I/2.

This differential double-ended voltage gain is equal in magnitude to the voltage gain of a single transistor amplifier with a load of RC and no external emitter resistance. The advantages of decreased temperature drift and good power supply rejection in critical applications, and a DC input reference of 0 V are typically far more important than the necessity of using an extra device, especially for IC chips.

The previous calculations for the differential pair assume there is no load across the output terminals. If this circuit drives a succeeding stage, the input impedance to this following stage will load the differential pair. One approach to this problem results from noting that when the collector of one BJT is driven positive by the input signal, the other collector moves an equal voltage in the opposite direction. Each end of the load resistor, RL, is driven in equal but opposite directions. The midpoint of the resistor is always at 0 V, for incremental signals. To calculate the loaded voltage gain, a resistance of RL/2 can be placed in parallel with each collector resistance to give an equivalent collector resistance of