Bipolar Junction Transistor Circuits:Basic Modeling

Basic Modeling

Simple electrical components such as resistors, capacitors, inductors, and independent voltage sources can be characterized in terms of their voltage versus current variation or V–I characteristics. For example, an ideal resistor has a model that exhibits a linear variation between voltage and current at all frequencies of operation. More complex devices can often be modeled in terms of these simpler components to allow easier analysis.

For devices such as transistors, there are generally two types of models. A large-signal model is used in most digital applications wherein the output voltage or current swing is quite large, approaching the power supply voltage. In amplifier applications, a small-signal model is used. The small-signal model assumes that all components of the model have fixed values resulting in linear operation, while the large-signal model may include components such as diodes that are highly nonlinear.

Prior to the availability of good circuit simulators, the large-signal models were linearized over certain regions to allow manual analysis to be done. Even earlier simulators were inefficient in solving nonlinear equations and piecewise linear models were often used to save expensive computation time. Later simulators applied more efficient methods of nonlinear equation solution and computing power became much less expensive. At the present time, the most popular simulators, based on Spice (simulation program for integrated circuit emulation), offer linearized models for small-signal circuits and nonlinear models for large-signal circuits.

Large-Signal Models

In some digital or switching applications, the operating point of the transistor may move from the cutoff region through the active region and into the saturation region. A model developed in the early 1950s is the Ebers–Moll model [4]. The Ebers–Moll model for an npn transistor is shown in Figure 10.5. This model, with certain additions, is still used in several modern computer simulators. This model implements the Ebers–Moll equations given by

here aF is the forward current gain from emitter to collector and aR the current gain from collector to emitter when operating in the inverted mode, that is, with the collector–base junction forward-biased and the emitter–base junction reverse-biased. Because of the geometry and doping of modern transistors, the value of aR might fall between 0.5 and 0.8 [2]. The parameters IES and ICS are constants at a given temperature that depend on the geometry and doping of the device.

The form of the equations often used for simulation programs [2] takes advantage of the fact that

where IS depends on geometry and doping of the base region at a given temperature. This now allows the Ebers–Moll equations to be expressed in terms of IS without requiring both IES and ICS.

The nonlinearities involved in the Ebers–Moll model make it very difficult to use in manual analysis. Simple piecewise linear models that change abruptly as the transistor moves into a different operating region are applied to perform approximate manual analysis. Often, when switching between saturation and cutoff takes place, the models of Figure 10.6 can be used to determine appropriate element values to be specified for succeeding simulations [5]. For the cutoff region, Figure 10.6(a) shows an open circuit between all terminals of the BJT. This is based on the Ebers–Moll model of Figure 10.5 assuming that the leakage currents of the reverse-biased junctions are zero. The saturation model of Figure 10.6(b) shows a small voltage source that represents the forward-biased voltage drop from base to emitter

To do more accurate simulations, the earlier computer models evolved to include second-order effects such as base-width modulation (Early effect), changes in b with low and high current levels, base resistance, collector-to-substrate, and other capacitive effects. The Gummel–Poon model, developed in 1970 [6], has been improved over the years and is available in many versions of the Spice simulator. With proper parameter values entered into the simulator, the accuracy of BJT simulation is excellent when using the modern Gummel–Poon model. Although MOSFET modeling has improved dramatically over the last decade, the simulation results for MOSFET circuits are generally not as accurate as those for BJT circuits.

Small-Signal Models

Most amplifier circuits constrain the BJT stages to active region operation. In such cases, the models can be assumed to have constant elements that do not change with signal swing. These models are linear models. The quiescent or bias currents are first found using a nonlinear model to allow the calculation of current-dependent element values for the small-signal model. For example, the dynamic resistance of the base–emitter diode, re, is given by

where IE is the DC emitter current. Once IE is found from a nonlinear DC equivalent circuit, the value of re is calculated and assumed to remain constant as the input signal is amplified.

The equivalent circuit [7] of Figure 10.7 shows the small-signal hybrid-p model that is closely related to the Gummel–Poon model and is used for AC analysis in the Spice program. The capacitance, C¹, accounts for the diffusion capacitance and the emitter–base junction capacitance. The collector–base junction capacitance is designated Cm. The resistance rp = (b +1)re . The transconductance, gm, is given by

In many high-frequency, discrete amplifier stages and in some high-frequency IC stages, a small value of load resistance will be used. Approximate hand analysis can then be done by neglecting the ohmic resistances, RE and RC along with CCS, the collector to substrate capacitance. If the impedance ro is much larger than the load resistance, RL, of the high-frequency amplifying stage, it can be considered as an open circuit. The resulting model that allows relatively viable hand analysis is shown in Figure 10.8(a).

For small values of load resistances, the effect of the capacitance can be represented by an input Miller capacitance that appears in parallel with Cp, resulting in a total capacitance of CT. This simplified circuit now includes two separate loops as shown in Figure 10.8(b) and is referred to as the unilatera equivalent circuit. Typically, the input loop limits the bandwidth of the amplifier stage. When driven with a signal generator having a source resistance of Rs, the upper 3-dB frequency can be approximated as

where A is the gain of the stage from point B¢ to the collector of the stage. Although Cm is small, the resulting Miller effect increases this value to the point that it can dominate the expression for upper 3-dB frequency. In any case, it often has a major effect on frequency performance.

When higher impedance loads are used in a BJT as is often the case for IC amplifier design, the Miller effect approach becomes less accurate and the performance must be simulated to achieve precise results. Silicon BJTs now have current gain bandwidth figures, ft, that exceed 12 GHz [2]. An amplifier stage constructed with such a device might have an upper corner frequency of 1 GHz.